| Patent application number | Description | Published |
|---|
| 20080222361 | PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS - A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. In some cases, phased access can be described as pipelined tag and information array access, though strictly speaking, indexing into the information array need not depend on results of the tag array access. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array. | 09-11-2008 |
| 20100207687 | CIRCUIT FOR A LOW POWER MODE - A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes. | 08-19-2010 |
| 20100306302 | TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND - A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings. | 12-02-2010 |
| 20110066918 | SOFT ERROR CORRECTION IN A MEMORY ARRAY AND METHOD THEREOF - A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other. | 03-17-2011 |
| 20110116328 | MEMORY DEVICE AND METHOD THEREOF - An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements. | 05-19-2011 |
| 20110119672 | Multi-Core System on Chip - A multi-core system on a chip ( | 05-19-2011 |
| 20110191602 | PROCESSOR WITH SELECTABLE LONGEVITY - A processor and method has at least one processor core for processing information and receives an operating voltage for powering circuitry of the processor. A selector receives a value indicative of a temperature within the processor and receives a value from a plurality of possible longevity values that each indicates a predetermined desired longevity of valid operation of the processor. An output provides an identifier that controls at least one of an operating voltage or an operating frequency of the processor, wherein the identifier provided is at least based on the value indicative of temperature and the predetermined desired longevity. A reliability storage device coupled to the selector stores the value from the plurality of possible longevity values that each indicates the predetermined desired longevity of valid operation of the processor. | 08-04-2011 |
| 20110265090 | MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING - A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. Accumulated usage information for a core of the plurality of processor cores is updated in response to a determined use of the core. | 10-27-2011 |
| 20110296211 | DATA PROCESSOR HAVING MULTIPLE LOW POWER MODES - A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal. | 12-01-2011 |
| 20120036398 | MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING - A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations. | 02-09-2012 |
| Patent application number | Description | Published |
|---|
| 20100129570 | Method for making artificial turf - An artificial athletic turf includes a backing having a top face and a bottom face, yarn tufted through the backing such that cut pile extends from the top face and backloops of yarn are closely adjacent the bottom face and a discontinuous coat is disposed over the backloops and bottom face in order to bind the yarn to the backing The coating material is sprayed onto the bottom face of the tufted backing at an inclination angle of less than 45 degrees to the plane of the backing and under conditions which cause sprayed material to bind the backloops to the backing, but not deposit along narrow areas of the backing between rows of backloops, thus, allowing the turf to remain porous in spots. | 05-27-2010 |
| 20100129571 | Method for making artificial turf - An artificial athletic turf includes a backing having a top face and a bottom face, yarn tufted through the backing such that cut pile extends from the top face and backloops of yarn are closely adjacent the bottom face and a porous coat is disposed over the backloops and bottom face in order to bind the yarn to the backing The coating material is sprayed, under high pressure and in distinct particles, onto the bottom face of the tufted backing under conditions which cause sprayed particles to rapidly cure and, therefore, partially cohere to each other in a porous network in which coating material generally is not accumulated between the backloops and backing face and does not fill a significant proportion of the fiber pores existent in the backing | 05-27-2010 |
| 20100319510 | Apparatus for collecting artificial turf for recycling - A turf collecting machine capable of automatically collecting laid artificial athletic turf, separating the infill and tufted backing components of the collected turf, and then depositing those separated components into separate storage containers is disclosed. The apparatus also includes mechanisms for cleaning the infill particles collected. | 12-23-2010 |
| Patent application number | Description | Published |
|---|
| 20080271886 | Downhole Gas Compressor - A method for producing gas from a well with low pressure involves running a bottom hole pressure test to graph a P-Q curve. The operator computes a frictional pressure drop due to friction of the gas flowing through the production tubing to the surface. A packer is set above perforations in the well. A screw pump is selected that has a capacity equal to the sum of the frictional pressure drop plus a desired wellhead pressure. The screw pump has a flow rate capacity determined from the P-Q curve. The operator may vary the frequency of a downhole motor to achieve the desired wellhead pressure. | 11-06-2008 |
| 20090044953 | Viscometer For Downhole Pumping - A submersible pumping system for use downhole, wherein the system includes a pump, an inlet section for receiving fluid, a pump motor, and a viscometer. Pumping system operating parameters are adjusted based on wellbore fluid viscosity measured by the viscometer. | 02-19-2009 |
| 20090272177 | Seal Section Assembly Mechanical Face Seal Integrity Verification Tool - A test device for testing the integrity of a seal has a clear t-shaped liquid reservoir with three ends. A guide adapter is connected to the first end of the liquid reservoir and extends axially therefrom along an axis of the reservoir. A shaft adapter is connected to the second end of the body, opposite the first end. A test shaft with first and second ends extends axially through the first and second ends of the body and test and shaft adapters along the axis. The first end of the shaft is adapted to be connected to the rotating shaft of pump assembly. | 11-05-2009 |
| 20100314103 | METHOD AND DEVICE FOR MAINTAINING SUB-COOLED FLUID TO ESP SYSTEM - A method of operating an electrical submersible pumping system that includes realtime monitoring of the wellbore fluid and adjusting pump speed so the fluid entering the pump remains subcooled. The method can include adding sensors within the wellbore and digitally storing fluid data accessible by a pump controller. The pump speed can be increased or decreased by adjusting the frequency of the electrical power delivered to the pump motor. | 12-16-2010 |
| 20110024124 | Caisson Two-Phase Emulsion Reducer - A seafloor pump assembly is installed within a caisson that has an upper end for receiving a flow of fluid containing gas and liquid. The pump assembly is enclosed within a shroud that has an upper end that seals around the pump assembly and a lower end that is below the motor and is open. A separating device is connected to an upper end portion of the discharge pipe within the caisson. The separating device causes separation of gas from the flow containing gas and liquid to be enhanced prior to the flow reaching the operating liquid level in the caisson. | 02-03-2011 |
| Patent application number | Description | Published |
|---|
| 20110105232 | Methods, Systems, and Products for Centralized Control of Gaming Applications - Methods, systems, and products provide centralized control of gaming applications. A request is received from a destination to store a status of a gaming application associated with a username. A bookmark is received that identifies a logical location in the gaming application. The bookmark is associated to the username and to the gaming application. A request is received for the status of the gaming application associated with the username. A query is made for the bookmark associated with the gaming application and with the username. The bookmark is sent to the destination, such that the destination may resume the gaming application from the bookmark. | 05-05-2011 |
| 20110292938 | System and Method of Redirecting Internet Protocol Traffic for Network Based Parental Controls - A method of redirecting traffic on a network includes receiving a subscriber request to use a parental control service, assigning to the subscriber's access device an Internet protocol (IP) address from a block of addresses reserved for the service, receiving a transaction, determining that the transaction is from an address in the block, and redirecting the transaction to a parental control device on the network. A network-based parental control system includes an access device for an account that uses a parental control service, a dynamic host configuration protocol server that assigns to the access device an IP address from a block of addresses reserved for the parental control service, a parental control policy device, and a router that receives a transaction from the access device, determines that the transaction is from an address in the block, and redirects the transaction to the parental control policy device. | 12-01-2011 |
| 20120023562 | SYSTEMS AND METHODS TO ROUTE NETWORK COMMUNICATIONS FOR NETWORK-BASED SERVICES - Example systems and methods to route network communications for network-based services are disclosed. An example method includes receiving network communications; determining if at least one of a source address or a destination address of the received network communications is associated with a customer to receive a network-based service; forwarding the network communications to a policy enforcement point if the at least one of the source address or the destination address is associated with the customer; determining if the forwarded network communications violates a policy selectively associated with the customer; and forwarding the network communications from the policy enforcement point to the destination address if the network communications is not in violation of the policy. | 01-26-2012 |
