Beak-Hyung
Beak-Hyung Cho, Gyeonggi-Do KR
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20090279351 | SEMICONDUCTOR MEMORY DEVICES AND METHODS HAVING CORE STRUCTURES FOR MULTI-WRITING - A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line. In a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, so that data writing time is reduced under the same conditions as a normal write mode. | 11-12-2009 |
20100097850 | APPARATUS AND SYSTEMS USING PHASE CHANGE MEMORIES - Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. | 04-22-2010 |
20100128516 | Nonvolatile Memory Devices Having Bit Line Discharge Control Circuits Therein that Provide Equivalent Bit Line Discharge Control - A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines. | 05-27-2010 |
20110242886 | Apparatus and Systems Using Phase Change Memories - Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. | 10-06-2011 |
Beak-Hyung Cho, Yongin-Si KR
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20090141567 | Semiconductor device having memory array, method of writing, and systems associated therewith - In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received. | 06-04-2009 |
20100131708 | Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith - In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address. | 05-27-2010 |
Beak-Hyung Cho, Osan-City KR
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20090059658 | MEMORY SYSTEM, MEMORY DEVICE AND APPARATUS INCLUDING WRITING DRIVER CIRCUIT FOR A VARIABLE RESISTIVE MEMORY - An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse. | 03-05-2009 |
Beak-Hyung Cho, Hwseong-Si KR
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20080232161 | RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF - A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage. | 09-25-2008 |