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Baylon

David M. Baylon, San Diego, CA US

Patent application numberDescriptionPublished
20090110066Method and Apparatus for Selecting a Coding Mode - A method and apparatus for selecting a coding mode for a block of a current picture are disclosed. For example, the method selects a coding mode in accordance with a cost function, for coding the block, wherein the cost function comprises a coding distortion parameter and a number of coding bits parameter, wherein said coding distortion parameter is measured in accordance with at least one of: between a prediction residual and a reconstructed prediction residual, or between a transformed prediction residual and a dequantized transformed prediction residual, wherein the number of coding bits parameter is computed in accordance with at least one of: from a true number of compressed bits resulting from coding said block, directly from a plurality of bins, or directly from a plurality of quantized transform coefficients.04-30-2009
20100061458METHOD AND APPARATUS FOR FAST MOTION ESTIMATION - Embodiments of the invention generally provide a method and apparatus for fast motion estimation. One embodiment of a method for motion estimation includes classifying a macroblock of a source frame in accordance with an initial matching cost, an intermediate matching cost, and a final matching cost, where the intermediate matching cost is estimated based on a predicted motion vector for the source frame and the final matching cost is estimated based on a final motion vector for a correlated macroblock in a prior frame, performing motion estimation for the macroblock based upon the classifying, wherein an early termination is applied in accordance with a result of the classifying, and outputting a motion vector for the macroblock based on a result of the motion estimation.03-11-2010
20100061459METHOD AND APPARATUS FOR COMPLEXITY-SCALABLE MOTION ESTIMATION - Embodiments of the invention generally provide a method and apparatus for complexity-scalable video coding. One embodiment of a method for video coding includes receiving a sequence of one or more video frames, obtaining a budget for the one or more video frames, the budget specifying a maximum number of computations that may be used in performing motion estimation for the one or more video frames, allocating the maximum number of computations among individual ones of the one or more video frames, performing motion estimation in accordance with the allocating, and outputting a motion estimate for the sequence.03-11-2010

Patent applications by David M. Baylon, San Diego, CA US

Joel Alonzo Baylon US

Patent application numberDescriptionPublished
20110038127MULTIPLE CHIP MODULE AND PACKAGE STACKING METHOD FOR STORAGE DEVICES - Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.02-17-2011

Joel Alonzo Baylon, Cavite PH

Patent application numberDescriptionPublished
20110161568MULTILEVEL MEMORY BUS SYSTEM FOR SOLID-STATE MASS STORAGE - The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.06-30-2011