Patent application number | Description | Published |
20080251419 | Apparatus and method for superheated vapor contacting and vaporization of feedstocks containing high boiling point and unvaporizable foulants in an olefins furnace - A contactor/separator is formed from a vessel; an inlet for receiving a vapor/liquid mixture; an inlet for receiving a superheated vapor; a hub located within the vessel, the hub including a plurality of vanes for imparting a centrifugal motion to the vapor/liquid mixture or the superheated vapor; an outlet in a bottom of the vessel for removing liquid; and an outlet for removing vapor from the vessel. A method is also provided for heating and separating liquid and vapor from a hydrocarbon feedstock comprising introducing a hydrocarbon feedstock into a contactor/separator: introducing a superheated vapor into the contactor/separator such that it contacts and vaporizes a portion of the feedstock within the contactor/separator; separating unvaporized feedstock from vaporized feedstock in the contactor/separator; removing the vaporized feedstock and the superheated vapor through a first outlet; and removing the unvaporized feedstock through a second outlet. | 10-16-2008 |
20090054716 | PROCESS FOR PRODUCING LOWER OLEFINS FROM HYDROCARBON FEEDSTOCK UTILIZING PARTIAL VAPORIZATION AND SEPARATELY CONTROLLED SETS OF PYROLYSIS COILS - A process for making lower olefins from a wide boiling range hydrocarbon feed by use of a combination of one or more vapor/liquid separation devices, and then pyrolytically cracking the vapor phase in separate sets of pyrolysis radiant tubes, thereby producing a higher level of lower olefin product. | 02-26-2009 |
20110036751 | APPARATUS AND METHOD FOR SUPERHEATED VAPOR CONTACTING AND VAPORIZATION OF FEEDSTOCKS CONTAINING HIGH BOILING POINT AND UNVAPORIZABLE FOULANTS IN AN OLEFINS FURNACE - A contactor/separator is formed from a vessel; an inlet for receiving a vapor/liquid mixture; an inlet for receiving a superheated vapor; a hub located within the vessel, the hub including a plurality of vanes for imparting a centrifugal motion to the vapor/liquid mixture or the superheated vapor; an outlet in a bottom of the vessel for removing liquid; and an outlet for removing vapor from the vessel. A method is also provided for heating and separating liquid and vapor from a hydrocarbon feedstock comprising introducing a hydrocarbon feedstock into a contactor/separator: introducing a superheated vapor into the contactor/separator such that it contacts and vaporizes a portion of the feedstock within the contactor/separator; separating unvaporized feedstock from vaporized feedstock in the contactor/separator; removing the vaporized feedstock and the superheated vapor through a first outlet; and removing the unvaporized feedstock through a second outlet. | 02-17-2011 |
20130001132 | METHOD AND APPARATUS FOR QUENCHING A HOT GASEOUS STREAM - The invention comprises a process for cracking liquid hydrocarbon feed to produce cracked gaseous hydrocarbons comprising feeding a liquid hydrocarbon feed stream to an olefins furnace; cracking the liquid hydrocarbon feed stream in the olefins furnace to produce a gaseous cracked effluent stream; feeding the cracked effluent from the olefins furnace to a primary transfer line heat exchanger (TLE) having two sections; injecting a first wetting fluid in a weight ratio of wetting fluid to hot gaseous effluent tangentially into the hot gaseous effluent stream at a particular location in the second section of the primary TLE; feeding the hot gaseous effluent stream exiting from the TLE to a separator; separating a separator bottoms stream comprising tar and heavier hydrocarbons and a separator product stream comprising an olefin product; and recovering an olefin product from the separator product stream. | 01-03-2013 |
Patent application number | Description | Published |
20090089730 | Scalable Dependent State Element Identification - Methods, systems and software products are provided to enhance the scalability of dependent state analysis element identification. In a method of partitioning a model representing a state machine, a variable is selected from the variables of the model, and a first set of variables are identified that support the selected variable. Then a second set of variables is identified that have overlapping support of the first set of variables. The second set of variables is a partition suitable for use in determining an overapproximation of the reachable states of the selected variable. | 04-02-2009 |
20090100385 | Optimal Simplification of Constraint-Based Testbenches - Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate. | 04-16-2009 |
20090300559 | Incremental Speculative Merging - An incremental speculative merge structure which enables the elimination of invalid merge candidates without requiring the discarding of the speculative merge structure and all verification results obtained upon that structure. Targets are provided for validating the equivalence of gates g | 12-03-2009 |
20100050145 | Optimizing a Netlist Circuit Representation by Leveraging Binary Decision Diagrams to Perform Rewriting - Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic. | 02-25-2010 |
20130007530 | VERIFYING CORRECTNESS OF REGULAR EXPRESSION TRANSFORMATIONS THAT USE A POST-PROCESSOR - A method for determining correctness of a transformation between a first finite state automaton (FSA) and a second FSA, wherein the first FSA comprises a representation of a regular expression, and the second FSA comprises a transformation of the first FSA includes determining a third FSA, the third FSA comprising a cross product of the second FSA and a post-processor; determining whether the first FSA and the third FSA are equivalent; and in the event that the first FSA is determined not to be equivalent to the third FSA, determining that the transformation between the first FSA and the second FSA is not correct. | 01-03-2013 |
Patent application number | Description | Published |
20080256499 | USING CONSTRAINTS IN DESIGN VERIFICATION - A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate. | 10-16-2008 |
20090049416 | Computer Program Product for Extending Incremental Verification of Circuit Design to Encompass Verification Restraints - An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist. | 02-19-2009 |
20110022373 | MODEL CHECKING OF LIVENESS PROPERTY IN A PHASE ABSTRACTED MODEL - Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example. | 01-27-2011 |
20140115548 | METHOD AND SYSTEM FOR INVARIANT-GUIDED ABSTRACTION - A computer-implemented method of invariant-guided abstraction includes a processor of a computing device generating one or more invariants corresponding to a design under verification by executing a proof algorithm with an input comprising at least a portion of the design and a specified resource limit. The method further includes deterministically assigning priority information to the one or more invariants generated and to components of the design referenced by said invariants. Finally, the method includes performing invariant-guided localization abstraction on the design model to generate an abstracted design model utilizing the assigned priority information as a localization hint that results in abstractions that are at least one of (a) smaller abstractions and (b) easier to verify abstractions. | 04-24-2014 |