Patent application number | Description | Published |
20090100286 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 04-16-2009 |
20090146691 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 06-11-2009 |
20100023796 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 01-28-2010 |
20100153654 | DATA PROCESSING METHOD AND DEVICE - In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory. | 06-17-2010 |
20100281235 | RECONFIGURABLE FLOATING-POINT AND BIT-LEVEL DATA PROCESSING UNIT - Blocks of fixed-point units in a reconfigurable data processing unit assist the efficient calculation of floating decimal point numbers by virtue of joint hardware functions permanently implemented within the block. | 11-04-2010 |
20120072699 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 03-22-2012 |
20120311301 | PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION - In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution. | 12-06-2012 |
20130042137 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 02-14-2013 |
20140208143 | Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply - A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies. | 07-24-2014 |
20140310466 | Multi-processor bus and cache interconnection system - A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method. | 10-16-2014 |
20140325175 | PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION - The present invention includes an integrated module including a plurality of data processing units including a memory device having processing instruction data stored therein. The processing instruction data including subconfiguration data for at least one of the data processing units, the subconfiguration data including a plurality of blocks. The integrated module further includes a barrier disposed between a first block and a second block of the plurality of blocks. Wherein, the data processing units process the processing instruction data from the memory device such that the barrier provides for the data processing units to observe a configuration sequence of the subconfiguration data. | 10-30-2014 |
20140359254 | Logical cell array and bus system - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 12-04-2014 |
20150026431 | Method of Processing Data with an Array of Data Processors According to Application ID - A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel. | 01-22-2015 |
20150033000 | Parallel Processing Array of Arithmetic Unit having a Barrier Instruction - A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel. | 01-29-2015 |