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Barwin
Clive Barwin, Temecula, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110285535 | Mobile Asset Security and Tracking System and Method - A mobile asset security, tracking and recovery system and method are disclosed. One or more radio frequency identification (RFID) tags each include an attachment mechanism for attaching to the mobile asset, and having a unique identifier that is continuously transmitted as a radio frequency signal upon activation. A server system receives, via a communications network, registration data from a client system, the registration data including at least description data describing the mobile asset and the unique identifier for each RFID tag attached to the mobile asset, the server system further generating a report of the mobile asset being lost or stolen, the report having at least the unique identifier for each RFID tag attached to the mobile asset. A detection unit receives, via the communications network, the report from the server system, the detection unit having an RFID sensor to sense for the radio frequency signal transmitted by activated RFID tags attached to the mobile asset within a geographical range of the radio frequency signal transmission. | 11-24-2011 |
David Barwin, Golden, CO US
| Patent application number | Description | Published |
|---|---|---|
| 20090133108 | SYSTEMS FOR SECURE AUTHENTICATION FOR NETWORK ACCESS - Systems and methods for authenticating the identity of a user over a network. The user must supply a removable physical medium such as CD, DVD, or memory stick that contains security information about the user and the user's account as well as a user identification and password. This information is verified before the user is allowed to access the account. | 05-21-2009 |
John E. Barwin, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20080265982 | METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 10-30-2008 |
| 20090153228 | STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 06-18-2009 |
| 20110107291 | DESIGN SYSTEM AND METHOD THAT, DURING TIMING ANALYSIS, COMPENSATES FOR REGIONAL TIMING VARIATIONS - Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such regional timing variations. Based on an initial placement of devices for an integrated circuit chip, regional variations in one or more physical conditions that impact device timing (e.g., polysilicon perimeter density, average distance of devices to a well edge, average reflectivity) are mapped. Then, using a table that associates different derating factors with different levels of the physical condition(s), derating factors are assigned to different regions on the map. Next, a timing analysis is performed such that, for each region, delay of any path within that region is derated by the assigned derating factor. The map information can also be used when establishing a final placement of the devices on the integrated circuit chip in order to optimize placement of critical paths. | 05-05-2011 |
| 20110173583 | METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF - A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit. | 07-14-2011 |