| Patent application number | Description | Published |
|---|
| 20090286381 | Protective Layer To Enable Damage Free Gap Fill - In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO | 11-19-2009 |
| 20100099271 | METHOD FOR IMPROVING PROCESS CONTROL AND FILM CONFORMALITY OF PECVD FILM - A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal. | 04-22-2010 |
| 20100261349 | UV TREATMENT FOR CARBON-CONTAINING LOW-K DIELECTRIC REPAIR IN SEMICONDUCTOR PROCESSING - A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas phase source of —CH | 10-14-2010 |
| 20100267231 | APPARATUS FOR UV DAMAGE REPAIR OF LOW K FILMS PRIOR TO COPPER BARRIER DEPOSITION - An apparatus and method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. A semiconductor substrate processing system may be configured to include degas and plasma pre-clean modules, UV process modules, copper diffusion barrier deposition modules and copper seed deposition modules such that the substrate is held under vacuum and is not exposed to ambient air after low k damage repair and before copper barrier layer deposition. Inventive methods provide for treatment of a damaged low-k dielectric on a semiconductor substrate with UV radiation to repair processing induced damage and barrier layer deposition prior breaking vacuum. | 10-21-2010 |
| 20100308463 | INTERFACIAL CAPPING LAYERS FOR INTERCONNECTS - Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion layers are formed by depositing a precursor layer of metal-containing material (e.g., material containing Al, Ti, Ca, Mg, etc.) over an exposed copper line, and converting the precursor layer to a passivated layer (e.g., nitridized layer). For example, a substrate containing exposed copper line having exposed Cu—O bonds is contacted with trimethylaluminum to form a precursor layer having Al—O bonds and Al—C bonds on copper surface. The precursor layer is then treated to remove residual organic substituents and to form Al—N, Al—H bonds or both. The treatment can include direct plasma treatment, remote plasma treatment, UV-treatment, and thermal treatment with a gas such as NH | 12-09-2010 |
| 20100317178 | REMOTE PLASMA PROCESSING OF INTERFACE SURFACES - Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal. | 12-16-2010 |
| 20100317198 | REMOTE PLASMA PROCESSING OF INTERFACE SURFACES - Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, and a remote plasma source configured to provide a remote plasma to the load lock. | 12-16-2010 |
| 20110045610 | UV TREATMENT FOR CARBON-CONTAINING LOW-K DIELECTRIC REPAIR IN SEMICONDUCTOR PROCESSING - A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas phase source of —CH | 02-24-2011 |
| 20110111533 | UV AND REDUCING TREATMENT FOR K RECOVERY AND SURFACE CLEAN IN SEMICONDUCTOR PROCESSING - Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers. | 05-12-2011 |
| 20110117678 | CARBON CONTAINING LOW-K DIELECTRIC CONSTANT RECOVERY USING UV TREATMENT - A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric and associated apparatus enables process induced damage repair. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metallization, post-planarization, or both. UV treatments can include an exposure of the subject low-k dielectric to a constrained UV spectral profile and/or chemical silylating agent, or both. | 05-19-2011 |
| 20110120377 | REMOTE PLASMA PROCESSING OF INTERFACE SURFACES - Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal. | 05-26-2011 |
| 20110133313 | HARDMASK MATERIALS - Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si | 06-09-2011 |
| 20110135557 | HARDMASK MATERIALS - Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si | 06-09-2011 |
| 20110151678 | NOVEL GAP FILL INTEGRATION - Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps. | 06-23-2011 |
