| Patent application number | Description | Published |
|---|
| 20080244189 | Method, Apparatus, System and Program Product Supporting Directory-Assisted Speculative Snoop Probe With Concurrent Memory Access - A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access. | 10-02-2008 |
| 20080247496 | Early HSS Rx Data Sampling - In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted. | 10-09-2008 |
| 20090177813 | Scalable Interface for a Memory Array - A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests. | 07-09-2009 |
| 20090268727 | Early header CRC in data response packets with variable gap count - A method is provided for processing a command issued by a processor over a bus. The method includes ( | 10-29-2009 |
| 20090268736 | Early header CRC in data response packets with variable gap count - A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus. | 10-29-2009 |
| 20090271532 | Early header CRC in data response packets with variable gap count - A method is provided for processing a command issued by a processor over a bus. The method includes ( | 10-29-2009 |
| 20090271578 | Reducing Memory Fetch Latency Using Next Fetch Hint - In one aspect, a processor is provided. The processor may include logic, coupled to the processor, and to issue a currently issued memory fetch over a processor bus. The currently issued memory fetch may include a next fetch hint that may include information about a next memory fetch. | 10-29-2009 |
| Patent application number | Description | Published |
|---|
| 20080222489 | APPARATUS FOR IMPLEMENTING PROCESSOR BUS SPECULATIVE DATA COMPLETION - A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data. | 09-11-2008 |
| 20090028073 | DATA CAPTURE TECHNIQUE FOR HGH SPEED SIGNALING - A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling. | 01-29-2009 |
| 20110206141 | IMPLEMENTING SERIAL LINK TRAINING PATTERNS SEPARATED BY RANDOM DATA - A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination. | 08-25-2011 |
| 20110208954 | IMPLEMENTING KNOWN SCRAMBLING RELATIONSHIP AMONG MULTIPLE SERIAL LINKS - A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data. | 08-25-2011 |
