| Patent application number | Description | Published |
|---|
| 20080244191 | Processor system management mode caching - In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described. | 10-02-2008 |
| 20080288798 | Power management of low power link states - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 11-20-2008 |
| 20090006658 | Deferring peripheral traffic with sideband control - In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface, wherein the USB device cooperate to defer one or more data traffic exchanges by passing control messages via a sideband communication link. Other embodiments may be described. | 01-01-2009 |
| 20090006704 | Deferring Peripheral traffic with sideband control - In some embodiments, a system comprises a host system comprising an industry standard interface, a peripheral device coupled to the host device via the industry standard interface, and logic in the host system to confirm that the host device supports an enhanced feature, identify at least one pin on the industry standard interface on which the enhanced feature may be implemented, enable support for the enhanced feature on the at least one pin, and route communication traffic associated with the enhanced feature to the at least one pin. Other embodiments may be described. | 01-01-2009 |
| 20090172434 | Latency based platform coordination - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 07-02-2009 |
| 20090172439 | SYSTEM AND METHOD FOR FAST PLATFORM HIBERNATE AND RESUME - In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described. | 07-02-2009 |
| 20090249103 | PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE - Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described. | 10-01-2009 |
| 20100023790 | CPU POWER MANAGEMENT BASED ON UTILIZATION WITH LOWEST PERFORMANCE MODE AT THE MID-UTILIZATION RANGE - A demand-based method and system of a processor power management is described. A processor is caused to enter a particular performance mode based on a first and a second utilization threshold. The particular performance mode includes at least a first performance mode, a second performance mode, and a third performance mode. The processor is caused to operate with a clock frequency in the third performance mode that is lower than the clock frequency of the processor in the first and second performance modes. | 01-28-2010 |
| 20100083013 | Various Methods and Apparatuses for Power States in a Controller - Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event. | 04-01-2010 |
| 20100125723 | METHOD AND SYSTEM TO ENABLE FAST PLATFORM RESTART - A method and system to perform a fast reset or restart of a platform by minimizing the hardware initialization of IO devices in the platform during a restart of the platform. The basic input/output system (BIOS) of the platform traps any software initiated reset request (SIRR) or warm reset. The BIOS restores the input/output (IO) devices coupled with the platform to their previous hardware state to avoid the full platform initialization when the SIRR is trapped. The restart of the platform can be performed in a fast manner as the full platform initialization is minimized. | 05-20-2010 |
| 20100162023 | METHOD AND APPARATUS OF POWER MANAGEMENT OF PROCESSOR - A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy. | 06-24-2010 |
| 20100169684 | DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed. | 07-01-2010 |
| 20100169685 | IDLE DURATION REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed. | 07-01-2010 |
| 20110078473 | LATENCY BASED PLATFORM COORDINATION - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 03-31-2011 |
