Patent application number | Description | Published |
20090128860 | ABLATIVE PRINTING - A system for adding data to a printed publication comprises a data source for providing the data, a processing circuit, and an energy source. The processing circuit is configured to retrieve the data from the data source and to control the energy source to at least partially ablate the printed publication based on the data. The data may be fixed and/or variable data. | 05-21-2009 |
20120206739 | SYSTEM AND METHOD FOR ADDING DATA TO A PRINTED PUBLICATON - Systems and methods for adding data to a printed publication are provided. One system comprises a data source for providing the data, a processing circuit, and an energy source. The processing circuit is configured to retrieve the data from the data source and to control the energy source to at least partially ablate the printed publication based on the data. The publication is printed by a web offset printing press as the substrate travels through a plurality of print units of the web offset printing press. The processing circuit is configured to control the energy source to ablate the printed publication in-line with its production on the print units. | 08-16-2012 |
20140104627 | SYSTEM AND METHOD FOR ADDING DATA TO A PRINTED PUBLICATION - Systems and methods for adding data to a printed publication are provided. One method includes receiving variable data and controlling an energy source to at least partially ablate the printed publication based on the variable data. The printed publication is printed on the substrate using the commercial printing press based on fixed data. Controlling the energy source to at least partially ablate the printed publication includes, after the printed publication has been printed on the substrate by the commercial printing press based on the fixed data, controlling the energy source to remove a portion of the printed publication based on the variable data. | 04-17-2014 |
20150243020 | SYSTEM AND METHOD FOR ADDING DATA TO A PRINTED PUBLICATION - Systems and methods for adding data to a printed publication are provided. One method includes receiving variable data and controlling an energy source to at least partially ablate the printed publication based on the variable data. The printed publication is printed on the substrate using the commercial printing press based on fixed data. Controlling the energy source to at least partially ablate the printed publication includes, after the printed publication has been printed on the substrate by the commercial printing press based on the fixed data, controlling the energy source to remove a portion of the printed publication based on the variable data. | 08-27-2015 |
Patent application number | Description | Published |
20120236651 | SYSTEM AND METHOD FOR DETERMINING DATA DEPENDENT NOISE CALCULATION FOR A FLASH CHANNEL - Disclosed is an system and method for determining a probability that a memory cell was programmed to a certain input level. An output level is received from a memory cell and a probability is determined that the output level corresponds to each of a plurality of programming levels. Each probability is determined as a function of the output level, a mean value of a distribution corresponding to the programming level, and a variance from the mean value with the variance being determined by a relative position of the output level with respect to the mean value. A probability value is generated as a function of the plurality of determined probabilities and then provided for use at a demodulator. | 09-20-2012 |
20120240006 | TRELLIS-CODED MODULATION IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE - A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells. | 09-20-2012 |
20120240007 | LDPC DECODING FOR SOLID STATE STORAGE DEVICES - A solid state storage device includes a flash memory and a controller configured to store data in the flash memory via a plurality of channels. The stored data is encoded using a low-density parity-check code. Hard-decision decoders are configured to decode encoded data received from the flash memory via respective channels of the plurality of channels using the low-density parity-check code and to provide decoded data to the controller in response to one or more read commands from the controller. A soft-decision decoder is configured to decode the encoded data received from the flash memory using the low-density parity-check code and to provide the decoded data to the controller in response to one of the plurality of hard-decision decoders failing to decode the encoded data. The encoded data is obtained by the soft-decision decoder using a plurality of read-retry operations. | 09-20-2012 |
20120240012 | APPARATUS AND METHOD FOR MULTI-MODE OPERATION OF A FLASH MEMORY DEVICE - Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode. | 09-20-2012 |
20130031301 | BACKEND ORGANIZATION OF STORED DATA - A data units received from a host system are divided and/or redistributed among a plurality of data payloads, wherein boundaries of the data units are not aligned with boundaries of the data payloads. The plurality of data payloads are encoded into a respective plurality of codewords, and the plurality of codewords stored in the flash memory. Boundaries of the codewords are aligned with boundaries of the pages in the flash memory. | 01-31-2013 |
20130047044 | OPTIMAL PROGRAMMING LEVELS FOR LDPC - The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided. | 02-21-2013 |
20130047045 | ERROR INDICATOR FROM ECC DECODER - The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided. | 02-21-2013 |
20130124945 | DYNAMIC LDPC CODE RATE SOLUTION - The subject technology includes adjusting an error correcting code rate in a solid-state drive. A first plurality of memory operations are performed on a flash memory device of the solid-state drive using a first code rate. During operation of the drive, a controller monitors an operating condition associated with one or more memory units of the flash memory device for a trigger event. On the trigger event, the first code rate is adjusted in accordance with the operating condition to produce a second code rate, and a second plurality of memory operations is performed on the flash memory device using the second code rate. | 05-16-2013 |
20130163327 | WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM - Aspects of the subject technology encompass a method for retrieving information stored in flash memory. In certain implementations, the method can include operations for reading a plurality of memory cells in a word line, generating a plurality of read signals based on the reading of the plurality of memory cells and identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in the word line. In certain aspects, the method can further include operations for generating an output for the first memory cell, wherein the output is based on the first and second read signals. A data storage system and article of manufacture are also provided. | 06-27-2013 |
20130163328 | INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES - Aspects of the subject technology relate to a method for reading information stored in a flash memory device. In some implementations, the method can include steps including, obtaining a first read signal of a first cell, wherein the first cell is located in a first word line and a first bit line in the flash memory device, obtaining a programming level of a second cell, wherein the second cell is located in a second word line and the first bit line, and wherein the second word line is adjacent to the first word line. In certain aspects, the method may further comprise steps for obtaining decoding information for the first cell based on the programming level of the second cell. A data storage system and article of manufacture are also provided. | 06-27-2013 |
20130212451 | REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM - A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component. | 08-15-2013 |
20130290612 | SOFT INFORMATION MODULE - A system and method for generating reliability information (aka “soft information”) from a flash memory device is disclosed. A plurality of memory cells are read by a data storage controller at a first read level to obtain a plurality of program values. On an error indicator being received in connection with reading the plurality of memory cells, the plurality of memory cells are read one or more times at one or more different read levels to categorize the plurality of memory cells into two or more cell program regions. A confidence value is then assigned to each memory cell based on a corresponding cell program region for the memory cell, the confidence value being representative of a likelihood that the memory cell is programmed to a corresponding program value read at the first read level. | 10-31-2013 |
20130318422 | READ LEVEL ADJUSTMENT USING SOFT INFORMATION - A method for calibrating read levels in a flash memory device is provided. The method includes receiving read information from flash memory in response to a read command, assigning soft information to the received read information, determining an error signal based on the assigned soft information, determining a read level offset based on the error signal, and adjusting a read level in the flash memory by the determined read level offset. | 11-28-2013 |
20150143194 | REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM - Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector. | 05-21-2015 |
Patent application number | Description | Published |
20150013057 | Self-Cleaning Toilet Assembly and System - Toilet assemblies having various embodiments of a cleaning system are described herein which include a toilet assembly and a cleaning system. The toilet assembly has a toilet bowl, a toilet tank, a flush valve, a rim inlet port and a rim flow path (which may be an isolated rim path) extending from an outlet of the flush valve to the rim inlet port. The cleaning system has a reservoir for holding a liquid cleaning agent having an outlet port in fluid communication with the interior space of the reservoir body; a housing to receive the reservoir; a supply conduit in fluid communication with the interior of the reservoir; a flow control device capable of controlling flow through the supply conduit; and a control system activatable by an actuator feature, wherein upon activation of the actuator feature, the control system is adapted to initiate a clean cycle by: operating the flow control device for a first period of time sufficient to deliver a dose of a liquid cleaning agent from the supply conduit to an interior space of the flush valve in a closed position, the flush valve configured for delivery of fluid to the rim inlet port, and operating the flush valve to open the flush valve to introduce flush water to carry the dose of a liquid cleaning agent through the rim inlet port into the toilet bowl. | 01-15-2015 |
20150013058 | Self-Cleaning Toilet Assembly and System - Toilet assemblies having various embodiments of a cleaning system are described herein which include a toilet assembly and a cleaning system. The toilet assembly has a toilet bowl, a tank, a flush valve, and a rim in fluid communication with the bowl through a rim flow path from an outlet of the flush valve to at least one rim outlet port. The flush valve is configured to operate in a flush actuation mode wherein the flush valve is able to provide flush water flow sufficient for the toilet assembly to initiate a flush siphon or provide a wash down flush and to operate in a cleaning actuation mode wherein the flush valve is only partially opened to allow for introduction of a cleaning agent and flush water mixture to the bowl that is insufficient to initiate a siphon but sufficient for cleaning the bowl. The cleaning system includes a reservoir for a liquid cleaning agent, a housing for the reservoir, a supply conduit for receiving fluid from within the reservoir and delivering it to a flush valve, a flow control device capable of controlling flow of cleaning agent and a control system activatable by an actuator feature to initiate a clean cycle by operating the flow control device to deliver a dose of cleaning agent to one or more rim outlets, and operating the flush valve in cleaning actuation mode to introduce flush water to carry the dose of cleaning agent through the at least one rim outlet port into the toilet bowl at a flow rate insufficient to initiate a siphon but sufficient for cleaning the bowl. | 01-15-2015 |