Patent application number | Description | Published |
20130294993 | Process and Apparatus for Treating a Gas Stream - A process of treating hydrogen gas liberated from the acid or alkaline dissolution of a metal is provided. The process comprises a step of passing the liberated hydrogen gas through a reactor containing an oxidising agent for oxidation of the hydrogen gas into water, followed by a step of regenerating the oxidising agent. Also provided is an apparatus for carrying out the process, the apparatus comprising a reactor containing the oxidising agent, wherein the reactor is at least partially immersed in an alumina bath. | 11-07-2013 |
20130312570 | Purification Process - A process for purifying Mo-99 from an acidic solution obtained by dissolving an irradiated solid target comprising uranium in an acidic medium, or from an acidic solution comprising uranium and which has previously been irradiated in a nuclear reactor, or from an acidic solution comprising uranium and which has been used as reactor fuel in a homogeneous reactor, the process comprising contacting the acidic solution with an adsorbent comprising a zirconium oxide, zirconium hydroxide, zirconium alkoxide, zirconium halide and/or zirconium oxide halide, and eluting the Mo-99 from the adsorbent using a solution of a strong base, the eluate then being subjected to a subsequent purification process involving an alkaline-based Mo-99 chromato-graphic recovery step on an anion exchange material. Also provided is apparatus for carrying out the process. | 11-28-2013 |
20140140462 | Process - A process for producing Tc-99m comprises the steps of contacting a solution of purified Mo-99 with an adsorbent material comprising i) a tin oxide, or ii) a zirconium oxide and a titanium oxide, such that the Tc-99m resulting from the decay of Mo-99 may thereafter be eluted. | 05-22-2014 |
20140234186 | Extraction Process - A process for extracting Cs-137 from i) an acidic solution obtained by dissolving an irradiated solid target comprising uranium, ii) an acidic solution comprising uranium which has previously been irradiated in a nuclear reactor, or iii) an acidic solution comprising uranium which has been used as reactor fuel in a homogeneous reactor, the acidic solution i), ii) or iii) having been treated to harvest Mo-99, wherein the process comprises contacting the treated acidic solution with an adsorbent comprising ammonium molybdophosphate (AMP). In an embodiment, the AMP is combined with an organic or inorganic polymeric support, for example AMP synthesised within hollow aluminosilicate microspheres (AMP-C). | 08-21-2014 |
Patent application number | Description | Published |
20090276542 | METHOD AND APPARATUS FOR TIME AND FREQUENCY TRANSFER IN COMMUNICATION NETWORKS - A timing system for time synchronization between a time server and a time client over a packet network. The timing system includes a time server for generating current timestamp information and a time client having a phase-locked loop driven client clock counter. The time client periodically exchanges time transfer protocol messages with the time server over the packet network, and calculates an estimated client time based on the timestamp information. The phase-locked loop in the time client receives periodic signals representing the estimated server time as its input and calculates a signal which represents the error difference between the estimated server time and the time indicated by the time client clock counter. The error difference eventually converges to zero or a given error range indicating the time presented by the client clock counter, which is driven by the phase-locked loop having locked onto the time of the time server. | 11-05-2009 |
20090323933 | Exponentiation method using multibase number representation - A method of scalar multiplication for use in elliptic curve-based cryptosystems (ECC) is provided. Scalars are represented using a generic multibase form combined with the non-adjacency property, which greatly reduces the nonzero density in the representation. The method allows for flexibly selecting an unrestricted number of bases and their weight in the representation according to the particular characteristics of a setting, in such a way that computing costs are minimized. A simple, memory-friendly conversion process from binary to multibase representation and an inexpensive methodology to protect the multibase scalar multiplication against simple-side channel attacks are also provided. | 12-31-2009 |
20100150117 | METHOD AND SYSTEM FOR WIRELESS LAN-BASED INDOOR POSITION LOCATION - A method and system for position location of clients in wireless local area networks. (WLANs). The position location technique utilizes time-of-flight (TOF) measurements of signals transmitted from a client to a number of wireless access points (APs) or vice versa to determine distances. Round-trip time (RTT) measurement protocols are used to estimate TOF and distances between the client at an unknown position and the WLAN APs. The method and system improves positioning accuracy by identifying and mitigating non-line-of sight (NLOS) errors such as multipaths. Trilateration algorithms are utilized in combination with median filtering of measurements to accurately estimate the position of the client. | 06-17-2010 |
20130282875 | METHOD AND APPARATUS FOR TIME AND FREQUENCY TRANSFER IN COMMUNICATION NETWORKS - A timing system for time synchronization between a time server and a time client. The timing system includes a time server for generating current timestamp information and a time client having a phase-locked loop driven client clock counter. The time client periodically exchanges time transfer protocol messages with the time server over a packet network, and calculates an estimated client time based on the timestamp information. The phase-locked loop in the time client receives periodic signals representing the estimated server time as its input and calculates a signal which represents the error difference between the estimated server time and the time indicated by the time client clock counter. The error difference eventually converges to zero or a given error range indicating the time presented by the client clock counter, which is driven by the phase-locked loop having locked onto the time of the time server. | 10-24-2013 |
Patent application number | Description | Published |
20080238214 | SWITCH GEAR CELL AND CONVERTER CIRCUIT FOR SWITCHING A MULTIPLICITY OF VOLTAGE LEVELS WITH A SWITCHGEAR CELL SUCH AS THIS - A switchgear cell having a group of connection is disclosed, with the group of connection having a first and a second controllable bidirectional power semiconductor switch and a capacitor. In order to reduce the stored electrical energy and to save space, the group of connection can have a third, fourth, fifth and sixth controllable bidirectional power semiconductor switch and the first controllable bidirectional power semiconductor switch can be connected back-to-back in series with the second controllable bidirectional power semiconductor switch, the third controllable bidirectional power semiconductor switch can be connected back-to-back in series with the fourth controllable bidirectional power semiconductor switch, the capacitor can be connected to the connection point of the first controllable bidirectional power semiconductor switch to the second controllable bidirectional power semiconductor switchand to the connection point of the third controllable bidirectional power semiconductor switch) to the fourth controllable bidirectional power semiconductor switch, the fifth controllable bidirectional power semiconductor switch can be connected to the connection point of the first controllable bidirectional power semiconductor switch to the second controllable bidirectional power semiconductor switch, and to the fourth controllable bidirectional power semiconductor switch, and the sixth controllable bidirectional power semiconductor switch can be connected to the connection point of the third controllable bidirectional power semiconductor switch to the fourth controllable bidirectional power semiconductor switch and to the second controllable bidirectional power semiconductor switch. | 10-02-2008 |
20090141455 | CIRCUIT ARRANGEMENT FOR ELECTRICALLY CONTROLLING POWER AND COOLING ARRANGEMENT - The disclosure relates to a circuit arrangement for electrically controlling power, comprising at least one power control device and at least one heat extraction device. The at least one extraction device is in thermal contact with the at least one power control device. The heat extraction device is arranged such that it can be clamped to a fixed predefined electric potential and electrically insulated by the at least one power control device. | 06-04-2009 |
20090231896 | CONVERTER CIRCUIT FOR SWITCHING A LARGE NUMBER OF SWITCHING VOLTAGE LEVELS - A converter circuit for switching a large number of switching voltage levels is specified, in which a first switching group is provided for each. Second switching groups are provided, each having a first, second, third, fourth, fifth and sixth drivable bidirectional power semiconductor switch and capacitor. The first drivable bidirectional power semiconductor switch is reverse-connected in series with the second drivable bidirectional power semiconductor switch, the third drivable bidirectional power semiconductor switch is reverse-connected in series with the fourth drivable bidirectional power semiconductor switch, the first drivable bidirectional power semiconductor switch is connected to the capacitor, the third drivable bidirectional power semiconductor switch is connected to the capacitor, the fifth drivable bidirectional power semiconductor switch is directly connected to the fourth drivable bidirectional power semiconductor switch, and the sixth drivable bidirectional power semiconductor switch is directly connected to the second drivable bidirectional power semiconductor switch. | 09-17-2009 |
Patent application number | Description | Published |
20110038181 | RESONANT CONVERTER HAVING OVER-CURRENT PROTECTION APPARATUS AND CONTROLLING METHOD THEREOF - The configurations of a DC/DC resonant converter and a controlling method thereof are provided. The proposed converter includes an over-current protection apparatus including a first switch element having a first and a second terminals, and a first voltage element having a negative terminal coupled to a positive terminal of a DC input voltage source and a positive terminal coupled to the second terminal of the first switch element. | 02-17-2011 |
20130242624 | POWER MODULE AND POWER CONVERSION APPARATUS - A power module, which is connected to a power source, includes a rectifying unit, a filtering unit and an inverter. The rectifying unit has three legs. The filtering unit is connected to the rectifying unit, and the inverter is connected to the filtering unit. One of the three legs has two switching elements connected in series, and another one of the three legs has two rectifying elements connected in series. In addition, a power conversion apparatus including the power module is also disclosed. | 09-19-2013 |
20130258729 | MEDIUM VOLTAGE POWER APPARATUS - A power apparatus includes power modules. Each of the power modules includes an input transformer and power cell units. The input transformer has at least one primary winding and a plurality of secondary windings, and the primary winding is electrically connected to an AC power source. The power cell units are connected in series with one phase output line to a multi-phase load, in which the power cell units are electrically connected to the secondary windings, respectively. | 10-03-2013 |
20140016380 | MULTI-LEVEL VOLTAGE CONVERTER - A multi-level voltage converter includes a multi-point converter circuit and at least one full bridge inverter circuit. The multi-point converter circuit is configured for converting a DC voltage into an intermediate multi-level voltage. The full bridge inverter circuit is electrically connected in series with the multi-point converter circuit and configured for receiving the intermediate multi-level voltage to generate a multi-level output voltage corresponding to a single phase output. | 01-16-2014 |
Patent application number | Description | Published |
20120146205 | Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Semiconductor Package Utilizing a Leadframe for Electrical Interconnections - Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes. | 06-14-2012 |
20130105958 | Compact Wirebonded Power Quad Flat No-Lead (PQFN) Package | 05-02-2013 |
20140061885 | Power Quad Flat No-Lead (PQFN) Package - Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes. | 03-06-2014 |
20140091449 | Power Quad Flat No-Lead (PQFN) Semiconductor Package with Leadframe Islands for Multi-Phase Power Inverter - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a U-phase output node situated on a first leadframe island of a leadframe, a V-phase output node situated on a second leadframe island of said leadframe, and a W-phase output node situated on a W-phase die pad of said leadframe. The first leadframe island can be on a first leadframe strip of the leadframe, where the first leadframe strip is connected to a U-phase die pad of the leadframe. The second leadframe island can be on a second leadframe strip of the leadframe, where the second leadframe strip is connected to a V-phase die pad of the leadframe. A first W-phase power switch is situated on the W-phase die pad. Furthermore, at least one wirebond is connected to the W-phase die pad and to a source of a second W-phase power switch. The W-phase die pad can be a W-phase output terminal of the PQFN package. | 04-03-2014 |
20140097498 | Open Source Power Quad Flat No-Lead (PQFN) Leadframe - According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is connected to a U-phase current sense terminal. The U-phase output strip can substantially traverse across the PQFN leadframe. Another U-phase power switch is situated on the PQFN leadframe with a source of the another U-phase power switch connected to the U-phase output strip of the PQFN leadframe. The PQFN leadframe can include a leadframe island within the U-phase output strip. At least one wirebond may be connected to the U-phase output strip. | 04-10-2014 |
20140097531 | Power Quad Flat No-Lead (PQFN) Package in a Single Shunt Inverter Circuit - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC. | 04-10-2014 |
20140103514 | Power Quad Flat No-Lead (PQFN) Package Having Bootstrap Diodes on a Common Integrated Circuit (IC) - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase inverter situated on a leadframe. The PQFN package further includes drivers situated on the leadframe and configured to drive the multi-phase inverter. The PQFN package also includes bootstrap diodes respectively coupled to the drivers. The bootstrap diodes are in a common integrated circuit (IC) that is situated on the leadframe. The common IC can include the drivers. The drivers can be high side drivers that are coupled to high side power switches of the multi-phase inverter. Also, the bootstrap diodes can be coupled to a supply voltage terminal of the PQFN package. Furthermore, the PQFN package can include wirebonds coupling the common IC to bootstrap supply voltage terminals of the PQFN package. | 04-17-2014 |
20140117517 | Power Quad Flat No-Lead (PQFN) Package Having Control and Driver Circuits - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase power inverter, a control circuit, and a driver circuit. The driver circuit is configured to drive the multi-phase power inverter responsive to a control signal from the control circuit. The multi-phase power inverter, the control circuit, and the driver circuit are each situated on a PQFN leadframe of the PQFN package. The control circuit and the driver circuit can be in a common integrated circuit (IC). Furthermore, the control circuit can be configured to reconstruct at least two phase currents of the multi-phase power inverter from a combined phase current. | 05-01-2014 |
20140117518 | Control and Driver Circuits on a Power Quad Flat No-Lead (PQFN) Leadframe - According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase and W-phase power switches situated on the PQFN leadframe and respectively connected to a U-phase output strip and a W-phase output pad of the PQFN leadframe. The PQFN leadframe further includes a common integrated circuit (IC) including a driver circuit and a control circuit where the common IC is connected to the U-phase output strip and to the W-phase output pad of the PQFN leadframe. The PQFN leadframe can also include a V-phase power switch situated on the PQFN leadframe where the V-phase power switch is connected to a V-phase output strip of the PQFN leadframe. | 05-01-2014 |
20140124890 | Semiconductor Package Having Multi-Phase Power Inverter with Internal Temperature Sensor - According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature. | 05-08-2014 |
20140126256 | Semiconductor Package Having an Over-Temperature Protection Circuit Utilizing Multiple Temperature Threshold Values - According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes an over-temperature protection circuit configured to reduce current through the power switches based on multiple temperature threshold values of the power switches and a sensed temperature of the power switches. The over-temperature protection circuit can be configured to enter first and second modes based on the multiple temperature threshold values and the sensed temperature, where the second mode reduces current through the power switches to a greater extent than the first mode. | 05-08-2014 |
20140127861 | Semiconductor Packages Utilizing Leadframe Panels with Grooves in Connecting Bars - According to an exemplary implementation, a method includes utilizing a leadframe panel comprising a plurality of leadframe modules, each of the plurality of leadframe modules having a leadframe pad. The leadframe panel has a plurality of bars each having a plurality of grooves, where the plurality of bars connect the plurality of leadframe modules. The method further includes attaching a device to the leadframe pad. The method also includes molding the leadframe panel while leaving a bottom of the leadframe pad exposed. Furthermore, the method includes sawing through the plurality of grooves of the plurality of bars to singulate the plurality of leadframe modules into separate packaged modules. | 05-08-2014 |
20150235932 | Compact Power Quad Flat No-Lead (PQFN) Package - Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost lead frames. | 08-20-2015 |