Patent application number | Description | Published |
20080238917 | Graphics hub subsystem for interfacing parallalized graphics processing units (GPUS) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus - A graphics hub subsystem for interfacing parallelized graphics processing units (GPUs) with the CPU of a PC-based computing system having a CPU interface module and a PC bus. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers. and graphics libraries. The graphics hub subsystem includes a hardware hub having a hub router for interfacing with the CPU interface module and the GPUs by way of the PC bus, distributing the stream of geometrical data and graphic commands among the GPUs, and transferring pixel data output from one or more of the GPUs during the composition of frames of pixel data corresponding to final images for display on the display surface. The subsystem also includes one or more software hub drivers, stored in the system memory. The CPU interface module provides an interface between one or more software hub drivers and the hardware hub. During system operation, the software hub drivers: (i) control the operation of the hardware hub, (ii) interact with the OS and graphic libraries, and (iii) forward the stream of geometrical data and graphic commands, or a portion thereof, to each GPU over the PC bus. | 10-02-2008 |
20110279462 | METHOD OF AND SUBSYSTEM FOR GRAPHICS PROCESSING IN A PC-LEVEL COMPUTING SYSTEM - A graphics processing subsystem for use in a computing system, including a plurality of GPUs operating according to time division mode of graphics parallelization. At least one of the GPUs is a display-designated GPU that is connectable to a screen for displaying images produced by the graphics processing subsystem, and at least one of the GPUs is a non-display-designated GPU. The subsystem includes a hardware hub having a router, and being located between a CPU of the computing system and the plurality of GPUs. For images to be generated and displayed on the screen, the router directs to the plurality of GPUs successively a stream of geometric data and graphics commands. The geometric data and graphics commands directed to a non-display-designated GPU are processed by the GPU into image pixel data associated with a frame, the image pixel data is then redirected to the router, the image pixel data is then redirected to the display-designated GPU, and the image pixel data is then displayed on the screen. Geometric data and graphics commands directed to the display-designated GPU are processed by the GPU into image pixel data associated with a frame, and the image pixel data is then displayed on the screen. | 11-17-2011 |
20140125682 | METHOD OF DYNAMIC LOAD-BALANCING WITHIN A PC-BASED COMPUTING SYSTEM EMPLOYING A MULTIPLE GPU-BASED GRAPHICS PIPELINE ARCHITECTURE SUPPORTING MULTIPLE MODES OF GPU PARALLELIZATION - A hub mechanism for use in a multiple graphics processing unit (GPU) system includes a hub routing unit positioned on a bus between a controller unit and multiple GPUs. The hub mechanism is used for routing data and commands over a graphic pipeline between a user interface and one or more display units. The hub mechanism also includes a hub driver for issuing commands for controlling the hub routing unit. | 05-08-2014 |
Patent application number | Description | Published |
20090177131 | GAIT MODULATION SYSTEM AND METHOD - An electrical stimulation orthosis and method therefor, the orthosis including: (a) an at least semi-rigid frame configured to substantially envelop a limb segment, the frame having at least one first complementary mechanical fastener associated therewith; (b) a surface electrical stimulation electrode assembly associated with, and supported by, the frame, the assembly having a surface stimulation electrode for contacting at least one stimulation point on the limb segment, the surface electrode assembly having an electrode base for electrically associating, via the frame, with a stimulator unit for providing a stimulation signal to the surface electrode, the electrode base having a top face for receiving the stimulation electrode, and a bottom face having at least one second complementary mechanical fastener, the first and second fasteners adapted for reversible attachment and detachment, at a plurality of locations on the frame, thereby enabling the electrical stimulation electrode assembly to be adjustably and reversibly positioned on the frame. | 07-09-2009 |
20100078339 | MULTIPLE CANDLESTICK ASSEMBLY - A multiple candlestick assembly comprising at least two aligned candlestick bodies sharing a common base, where the candlestick bodies and the common base are integrally connected and co-molded. Also disclosed is a kit that includes a plurality of multiple candlestick assemblies of a varying number of aligned candlestick bodies. | 04-01-2010 |
20100168622 | SENSOR DEVICE FOR GAIT ENHANCEMENT - A foot sensor device and method for gait enhancement, the device including: (a) a sensor unit having a casing, the sensor unit for disposing within a shoe of a user, the sensor unit for sensing a parameter associated with a gait event; (b) an electronic communication unit, electrically associated with the sensor unit, for receiving a signal pertaining to the parameter, the electronic unit having: (i) a microcontroller; (ii) a transmitting unit for transmitting, in a wireless fashion, gait information based on the signal, to a unit of an orthosis external to the foot sensor device, and (iii) a housing for housing at least one of the microcontroller and the transmitting unit, and (c) a fastening unit, attached to the housing, adapted to fasten on to the shoe, so as to secure the communication unit in a fixed position during gait. | 07-01-2010 |
20110152968 | ORTHOSIS FOR A GAIT MODULATION SYSTEM - A functional electrical stimulation (FES) orthosis for FES to a limb segment, including: (a) a semi-rigid, self-retaining C-shaped frame, the frame configured to substantially envelop the limb segment, the frame including a first flexible and elongated circumferentially retaining element and at least a first and a second opposing flexible and elongated circumferentially retaining elements disposed on the circumferentially opposite side of the frame, the first retaining element and the first opposing retaining element forming a pair of opposing retaining elements, and (b) a surface electrical stimulation electrode for contacting at least one stimulation point on a surface of the limb segment, associated with, and supported by, the frame, the surface electrode for electrically associating, via the frame, with a neuroprosthetic stimulator unit, so as to provide FES, wherein the opposing retaining elements are configured to be radially spring-loaded towards a center of the frame, such that in donning the orthosis around the limb segment, the limb segment applies a counter-pressure from within the frame, against the opposing retaining elements, such that the orthosis is firmly and fixedly self-retained in a pre-determined position on the surface. | 06-23-2011 |
20120203156 | ADJUSTABLE ORTHOSIS FOR ELECTRICAL STIMULATION OF A LIMB - Systems, devices and methods for treating a targeted body tissue (e.g., bone, soft tissue, muscle, ligaments, etc.) by stimulating the body tissue with an electric current are described herein. In one embodiment, an apparatus includes a first orthosis member that includes a first electrode. The first orthosis member is configured to be disposed about a first portion of a limb of a user of the apparatus such that the first electrode is in contact with the first portion of the limb. The apparatus includes a second orthosis member that includes a second electrode. The second orthosis member is configured to be disposed about a second portion of the limb such that the second electrode is in contact with the second portion of the limb. A connector is configured to couple the second orthosis member to the first orthosis member and the connector has a selectively adjustable length. | 08-09-2012 |
20120330375 | ORTHOSIS FOR GAIT MODULATION - A functional electrical stimulation (FES) orthosis, including: a frame, an inner layer coupled to an inner surface of the frame, an electrode base, and a connector assembly. The frame is configured to substantially envelop a limb, and includes a retention portion configured to retain the frame about the limb, and a mounting portion configured to be coupled to an electrical stimulator. The electrode base is coupled to the inner layer, and is configured to couple a surface electrode to the inner layer. The frame and the inner layer are configured such that the electrode base is disposed at a predetermined position relative to the limb. The connector assembly is configured to electrically couple the stimulator to the electrode base. At least a portion of the connector assembly is disposed within a connector opening defined by the frame. | 12-27-2012 |
20120330395 | GAIT MODULATION SYSTEM AND METHOD - Methods related to an electrical stimulation orthosis are disclosed herein. In some embodiments, a method includes disposing a connector of a stimulation electrode assembly through an opening defined by a detachable layer. The connector of the stimulation electrode assembly is reversibly coupled to a connector disposed on an inner face of a frame. The detachable layer is coupled to the inner face of the frame. The method further includes disposing the frame about a limb segment of a body such that the detachable layer is in contact with a portion of the limb segment, and an electrical stimulation electrode of the stimulation electrode assembly is in contact with at least one stimulation point on a surface of the body associated with at least one of a nerve or a muscle. | 12-27-2012 |
20140303705 | ORTHOSIS FOR A GAIT MODULATION SYSTEM - A functional electrical stimulation (FES) orthosis for FES to a limb segment, including: (a) a semi-rigid, self-retaining C-shaped frame, the frame configured to substantially envelop the limb segment, the frame including a first flexible and elongated circumferentially retaining element and at least a first and a second opposing flexible and elongated circumferentially retaining elements disposed on the circumferentially opposite side of the frame, the first retaining element and the first opposing retaining element forming a pair of opposing retaining elements, and (b) a surface electrical stimulation electrode for contacting at least one stimulation point on a surface of the limb segment, associated with, and supported by, the frame, the surface electrode for electrically associating, via the frame, with a neuroprosthetic stimulator unit, so as to provide FES, wherein the opposing retaining elements are configured to be radially spring-loaded towards a center of the frame, such that in donning the orthosis around the limb segment, the limb segment applies a counter-pressure from within the frame, against the opposing retaining elements, such that the orthosis is firmly and fixedly self-retained in a pre-determined position on the surface. | 10-09-2014 |
20150273205 | GAIT MODULATION SYSTEM AND METHOD - An electrical stimulation orthosis and method therefor, the orthosis including: (a) an at least semi-rigid frame configured to substantially envelop a limb segment, the frame having at least one first complementary mechanical fastener associated therewith; (b) a surface electrical stimulation electrode assembly associated with, and supported by, the frame, the assembly having a surface stimulation electrode for contacting at least one stimulation point on the limb segment, the surface electrode assembly having an electrode base for electrically associating, via the frame, with a stimulator unit for providing a stimulation signal to the surface electrode, the electrode base having a top face for receiving the stimulation electrode, and a bottom face having at least one second complementary mechanical fastener, the first and second fasteners adapted for reversible attachment and detachment, at a plurality of locations on the frame, thereby enabling the electrical stimulation electrode assembly to be adjustably and reversibly positioned on the frame. | 10-01-2015 |
Patent application number | Description | Published |
20090172247 | CONTROLLER FOR ONE TYPE OF NAND FLASH MEMORY FOR EMULATING ANOTHER TYPE OF NAND FLASH MEMORY - A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller. | 07-02-2009 |
20110199823 | PRELOADING DATA INTO A FLASH STORAGE DEVICE - Programmer's data that is transferred from a programming device ( | 08-18-2011 |
20110228604 | PRELOADING DATA INTO A FLASH STORAGE DEVICE - Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous data bits in the programmer's data is calculated. If the programmer's data includes an uncorrectable number of erroneous data bits, the programmer's data is iteratively reread by using unconventional read reference voltages with decreased levels. The iteration process, which includes decreasing the level of the read reference voltages and recalculating the number of erroneous data bits, is terminated when the number of erroneous data bits in the programmer's is less than or equals a predetermined number of erroneous data bits, after which the storage device restores the programmer's data and conventionally rewrites it into the memory device. | 09-22-2011 |
20110271045 | Controller for One Type of NAND Flash Memory for Emulating Another Type of NAND Flash Memory - A method of executing an erasing instruction to erase host data from a flash memory device is provided. The method initiates with receiving from a host device an erase instruction to erase host data from an array of NAND flash memory cells grouped into separately-erasable device blocks, each device block including multiple device pages, the host data being a portion of device data that is stored in a device block. The host data is marked as erased, and a message is sent to the host device indicating that the host data has been erased. | 11-03-2011 |
20130024611 | Controller for One Type of NAND Flash Memory for Emulating Another Type of NAND Flash Memory - A method of executing reading instruction to read host data from a flash memory device is provided. The method initiates with receiving from a host device a read instruction to read host data from an array of NAND flash memory cells grouped into separately-readable device pages, the host data being a portion of device data that is stored in a device page. The host data is parsed from device data, and the parsed host data is sent to the host device. | 01-24-2013 |
20130159599 | Systems and Methods for Managing Data in a Device for Hibernation States - The present application is directed to systems and methods for managing data in a device for hibernation states. In one implementation, the device includes an interface and a processor. The interface is coupled with a first memory and a second memory. The processor is in communication with the first and second memories via the interface. The processor is configured to read first data from the first memory, generate image data of the data stored in the first memory based on the first data, and write to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory. The processor is further configured to, after the device awakes from the initial hibernation state, read the image data from the second memory, reconstruct the first data based on the image data, and write the first data to the first memory. | 06-20-2013 |
20150220268 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |
20150220550 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |
20150220551 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |
20150220552 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |