| Patent application number | Description | Published |
|---|
| 20080231312 | Structure for modeling stress-induced degradation of conductive interconnects - A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via. | 09-25-2008 |
| 20090014884 | SLOTS TO REDUCE ELECTROMIGRATION FAILURE IN BACK END OF LINE STRUCTURE - A back-end of the line (BEOL) structure and method are disclosed. In one embodiment the BEOL structure may include: a copper line in an ultra low-k dielectric, the copper line connected on one end to a cathode via and on another end to an anode via; and a plurality of slots extending laterally along a length of the copper line, the plurality of slots being non-continuous along the length of the copper line, and wherein the plurality of slots reduce electromigration failure in the BEOL structure by enabling copper extrusions to occur along the plurality of slots. | 01-15-2009 |
| 20090302476 | Structures and Methods to Enhance CU Interconnect Electromigration (EM) Performance - The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect. | 12-10-2009 |
| 20100164116 | ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT - A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations. | 07-01-2010 |
| 20100176514 | INTERCONNECT WITH RECESSED DIELECTRIC ADJACENT A NOBLE METAL CAP - The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap. | 07-15-2010 |
| 20110115508 | DETERMINING CRITICAL CURRENT DENSITY FOR INTERCONNECT - Solutions for determining a critical current density of a line are disclosed. In one embodiment a method of determining a critical current density in a line includes: applying a temperature condition to each of a plurality of samples including the line; calculating a cross-sectional area of the line for each of the plurality samples using data about an electrical resistance of the line over each of the temperature conditions; measuring an electrical current reading through the line for each of the plurality of samples; determining a current density through the line for each of the plurality of samples by dividing each electrical current reading by each corresponding cross-sectional area; determining an electromigration (EM) failure time for each of the plurality of samples; and determining the critical current density of the line using the current density and the plurality of EM failure times. | 05-19-2011 |
