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Bang, Yongin-Si
Doo-Jin Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080304844 | LIGHT SCANNING UNIT AND IMAGE FORMING APPARATUS EMPLOYING THE SAME - A light scanning unit of an image forming apparatus, the light scanning unit including: a base frame comprising a metal material to prevent the base frame from expanding and/or contracting due to an ambient temperature change; one or more mounting members provided in the base frame; and one or more optical elements mounted on the base frame by the one or more mounting members, the one or more optical elements generating and/or scanning a light beam. | 12-11-2008 |
| 20110135339 | APPARATUS AND METHOD FOR CONTROLLING POWER OF LASER DIODE HAVING OPTICAL POWER COMPENSATION - An apparatus includes an output voltage sensing unit, which senses an output voltage of a laser diode, which has been sampled during a power control period and transmits the sensed output voltage of the laser diode to an output voltage control unit; the output voltage control unit, which obtains an error voltage between a reference voltage and the sensed output voltage of the laser diode and generates a control voltage by proportionally integrating the error voltage; and an optical power compensation unit, which receives the control voltage and generates a compensated control voltage by compensating for an optical power deviation on the photosensitive drum during the printing period. | 06-09-2011 |
Hyo Jeong Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100099884 | METHOD OF PREPARING S-(-)-AMLODIPINE OR A SALT THEREOF AND AN INTERMEDIATE USED THEREIN - The present invention provides a novel method for preparing S-(−)-amlodipine having a high optical purity or a salt thereof and an intermediate used therein. | 04-22-2010 |
Ji-Hoon Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090193238 | Reconfigurable apparatus and method for providing multiple modes - A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includes: at least one reconfigurable operation mode execution unit performing a plurality of operations for processing a predetermined operation mode; a common coarse-grained array unit shared temporally by the at least one reconfigurable operation mode execution unit, and performing a main processing operation set to be performed by the common coarse-grained array unit, among the plurality of operations; and a controller determining whether the common coarse-grained array unit is available, and according to the result of the determination controlling the at least one reconfigurable operation mode execution unit so that the common coarse-grained array unit or an exclusive coarse-grained array unit performs the main processing operation, the exclusive coarse-grained array unit included in the at least one reconfigurable operation mode execution unit. Therefore, it is possible to reduce a delay time for data processing while reducing the size of hardware. | 07-30-2009 |
Jin-Min Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100079629 | APPARATUS AND METHOD FOR CORRECTING DEFECTIVE PIXEL - Disclosed is an apparatus for correcting a value of a defective pixel based on values of neighboring pixels of the defective pixel, the apparatus includes a plurality of first-stage median filters for receiving a value of a target pixel and values of neighboring pixels of the target pixel, and outputting median values of the received values; and at least one second-stage median filter for receiving the value of the target pixel and the median values from the first-stage median filters, and outputting a median value of the values received by the second-stage median filter. | 04-01-2010 |
Jin-Young Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110103781 | SHAKE CORRECTION APPARATUS IN DIGITAL CAMERA - A shake correction apparatus for correcting shake of a camera includes: a lens support plate including a correction lens and driven in a perpendicular direction with respect to an optical axis; and a position fixing member that decouplably couples with the lens support plate and fixes a position of the lens support plate according to a rotation of the lens support plate. | 05-05-2011 |
| 20120105960 | OPTICAL DEVICE INCLUDING ADJUSTABLE OPTICAL ELEMENT - An optical device includes an optical element through which light is transmitted, a frame that supports the optical element, magnets in the frame around the optical element, a base unit that movably supports the frame, a cover unit to cover the magnets, and magnetic force generating units in the cover unit in positions corresponding to the magnets and that generate magnetic force when an electrical signal is applied. | 05-03-2012 |
Jong-Min Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100302877 | MEMORY DEVICE HAVING REDUCED STANDBY CURRENT AND MEMORY SYSTEM INCLUDING SAME - A memory device includes a plurality of banks, a first generator generating standby current in response to a standby signal, and a switching circuit supplying the standby current to at least one of the plurality of banks in response to a plurality of active signals. | 12-02-2010 |
Sam-Young Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090251181 | Method and apparatus for tuning phase of clock signal - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 10-08-2009 |
| 20100008169 | Latency Control Circuit and Method Thereof and an Auto-Precharge Control Circuit and Method Thereof - A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal. | 01-14-2010 |
| 20110158030 | METHOD AND APPARATUS FOR TUNING PHASE OF CLOCK SIGNAL - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 06-30-2011 |
Seok-Hoon Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100164627 | COMPARATOR CIRCUIT FOR COMPARING THREE INPUTS - A comparator circuit. A comparator circuit may include a differential amplifying unit to amplify a difference between a voltage at a first node and a voltage at a second node and/or output a resultant voltage, and/or a current source to supply a first bias current to a first node and/or supply a second bias current to a second node. A comparator may include a first bias switch to bias a current flowing from a first node to a ground voltage source, a second bias switch to bias a part of a current flowing from a second node to a ground voltage source, a third bias switch to bias a remaining part of a current flowing from a second node to a ground voltage source, and/or a bias converting unit to supply a third bias current to a second node. | 07-01-2010 |
| 20100164679 | INTEGRATED CIRCUIT INCLUDING A FUSING CIRCUIT CAPABLE FOR PROTECTING A FUSING SPARK - An integrated circuit includes a first inner circuit including at least one first semiconductor device, a second inner circuit including at least one second semiconductor device, and a fusing circuit connected between the first inner circuit and the second inner circuit to perform a fusing operation which electrically disconnects the first inner circuit from the second inner circuit through a fusing voltage. The fusing circuit bypasses a spark current occurring during the fusing operation to a ground power source so as not to flow the spark current into the first inner circuit and the second inner circuit. | 07-01-2010 |
Seok-Won Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080249732 | System, method and medium calibrating gyrosensors of mobile robots - Provided are a system, method and medium calibrating a gyrosensor of a mobile robot. The system includes a camera to obtain image data of a fixed environment, a rotation angle calculation unit to calculate a plurality of angular velocities of a mobile robot based on an analysis of the image data, a gyrosensor to output a plurality of pieces of raw data according to rotation inertia of the mobile robot and a scale factor calculation unit to calculate a scale factor that indicates the relationship between the pieces of raw data and the angular velocities. | 10-09-2008 |
Sukchul Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120039564 | Photoelectric Integrated Circuit Devices And Methods Of Forming The Same - A photoelectric integrated circuit device may include a substrate including an electronic device region and an on die optical input/output device region, the substrate having a trench in the on die optical input/output device region; a lower clad layer provided in the trench, the lower clad layer having an upper surface lower than a surface of the substrate; a core provided on the lower clad layer; an insulating pattern provided on the core; an optical detection pattern provided on the insulating pattern, the optical detection pattern having at least a portion provided in the trench; and at least one transistor provided on the substrate of the electronic device region. | 02-16-2012 |
Suk-Chul Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100065912 | STACKED SEMICONDUCTOR DEVICE AND RELATED METHOD - A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench. | 03-18-2010 |
| 20110318922 | METHOD OF FORMING SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 12-29-2011 |
| 20110318923 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME INCLUDING A CONDUCTIVE STRUCTURE IS FORMED THROUGH AT LEAST ONE DIELECTRIC LAYER AFTER FORMING A VIA STRUCTURE - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 12-29-2011 |
| 20120043666 | Semiconductor Device and Method of Fabricating the Same - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 02-23-2012 |
Won-Chul Bang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120113030 | APPARATUS AND METHOD FOR CONTROLLING TERMINAL - An apparatus and method for controlling a terminal is provided. A terminal control apparatus may set a virtual display space in an outer circumferential portion of the terminal and map at least one file to the virtual display space. Through this, a display region of the terminal may be expanded to an outer circumferential region of the terminal. | 05-10-2012 |