| Patent application number | Description | Published |
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| 20100133104 | Fluid processing device including size-changing barrier - A diagnostic device is provided that includes a plurality of retainment regions interconnected through at least one fluid processing passageway or separated by at least one barrier. A fluid flow modulator can be provided in the fluid processing passageway if a fluid processing passageway is provided. The barrier and/or fluid flow modulator can comprise a polysaccharide, a derivative of a polysaccharide, or a combination thereof. For example, the barrier can comprise a chitosan material. | 06-03-2010 |
| 20100136701 | Device including a dissolvable structure for flow control - A diagnostic device is provided that includes a plurality of retainment regions, with the retainment regions that are separated by at least one dissolvable barrier. The retainment regions can be interconnected through at least one fluid processing passageway. A retainment region can include a container such as a retainment region, well, chamber, or other receptacle, or a retainment region such as a surface on which the material is retained. The retainment regions can include a reaction retainment region, one or more reagent retainment regions, each containing unreacted reagents, and a sample retainment region. A pressure-actuated valve can be positioned in each fluid processing passageway interconnecting the one or more reagent retainment regions with the respective intermediate retainment regions interposed between each of the one or more reagent retainment regions and the reaction retainment region. The dissolvable barrier can be a fluid flow modulator in the at least one fluid processing passageway. | 06-03-2010 |
| 20100236930 | Electrowetting Dispensing Devices and Related Methods - A method for dispensing liquid for use in biological analysis may comprise positioning liquid to be dispensed via electrowetting. The positioning may comprise aligning the liquid with a plurality of predetermined locations. The method may further comprise dispensing the aligned liquid from the plurality of predetermined locations through a plurality of openings respectively aligned with the predetermined locations. The dispensing may be via electrowetting. | 09-23-2010 |
| 20110114206 | Fluid Processing Device Including Size-Changing Barrier - A diagnostic device is provided that includes a plurality of retainment regions interconnected through at least one fluid processing passageway or separated by at least one barrier. A fluid flow modulator can be provided in the fluid processing passageway if a fluid processing passageway is provided. The barrier and/or fluid flow modulator can comprise a polysaccharide, a derivative of a polysaccharide, or a combination thereof. For example, the barrier can comprise a chitosan material. | 05-19-2011 |
| 20110126913 | Device Including A Dissolvable Structure For Flow Control - A diagnostic device is provided that includes a plurality of retainment regions, with the retainment regions that are separated by at least one dissolvable barrier. The retainment regions can be interconnected through at least one fluid processing passageway. A retainment region can include a container such as a retainment region, well, chamber, or other receptacle, or a retainment region such as a surface on which the material is retained. The retainment regions can include a reaction retainment region, one or more reagent retainment regions, each containing unreacted reagents, and a sample retainment region. A pressure-actuated valve can be positioned in each fluid processing passageway interconnecting the one or more reagent retainment regions with the respective intermediate retainment regions interposed between each of the one or more reagent retainment regions and the reaction retainment region. The dissolvable barrier can be a fluid flow modulator in the at least one fluid processing passageway. | 06-02-2011 |
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| 20100038689 | INTEGRATING FABRICATION OF PHOTODETECTOR WITH FABRICATION OF CMOS DEVICE ON A SILICON-ON-INSULATOR SUBSTRATE - A method and semiconductor device for integrating the fabrication of a photodetector with the fabrication of a CMOS device on a SOI substrate. The SOI substrate is divided into two regions, a CMOS region and an optical detecting region. After the CMOS device is fabricated in the CMOS region, the optical detecting region is patterned and etched through the top silicon layer and the buried oxide layer to the base silicon layer. The pattern is etched to a depth so that after a material of a photodetector is deposited in the etched pattern, the material grows to the surface level of the SOI substrate. After the formation of a photodetector structure in the optical detecting region, the metallization process is performed on the CMOS device and the photodetector. In this manner, the fabrication of a photodetector is integrated with the fabrication of a CMOS device on the SOI substrate. | 02-18-2010 |
| 20100181655 | ESTABLISHING A UNIFORMLY THIN DIELECTRIC LAYER ON GRAPHENE IN A SEMICONDUCTOR DEVICE WITHOUT AFFECTING THE PROPERTIES OF GRAPHENE - A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene. | 07-22-2010 |
| 20100207101 | INCORPORATING GATE CONTROL OVER A RESONANT TUNNELING STRUCTURE IN CMOS TO REDUCE OFF-STATE CURRENT LEAKAGE, SUPPLY VOLTAGE AND POWER CONSUMPTION - A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode. | 08-19-2010 |
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| 20090199151 | ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION - An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic. | 08-06-2009 |
| 20100122231 | ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS - A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip. | 05-13-2010 |
| 20100269079 | Analyzing Multiple Induced Systematic and Statistical Layout Dependent Effects On Circuit Performance - A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions. | 10-21-2010 |
| 20100333049 | Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography - Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit. | 12-30-2010 |
| 20110119642 | Simultaneous Photolithographic Mask and Target Optimization - A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements. | 05-19-2011 |
| 20110150343 | Optical Proximity Correction for Transistors Using Harmonic Mean of Gate Length - A mechanism is provided for harmonic mean optical proximity correction (HMOPC). A lithographic simulator in a HMOPC mechanism generates an image of a mask shape based on a target shape on a wafer thereby forming one or more lithographic contours. A cost function evaluator module determines a geometric cost function associated with the one or more lithographic contours. An edge movement module minimizes the geometric cost function thereby forming a minimized geometric cost function. The edge movement module determines a set of edge movements for each slice in a set of slices associated with the one or more lithographic contours using the minimized geometric cost function. The edge movement module moves the edges of the mask shape using the set of edge movements for each slice in the set of slices. The HMOPC mechanism then produces a clean mask shape using the set of edge movements. | 06-23-2011 |
| 20110154280 | PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY - An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape. | 06-23-2011 |
| 20120040280 | Simultaneous Optical Proximity Correction and Decomposition for Double Exposure Lithography - A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative. | 02-16-2012 |
