| Patent application number | Description | Published |
|---|
| 20080237710 | Localized spacer for a multi-gate transistor - In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed. | 10-02-2008 |
| 20090017589 | TRI-GATE INTEGRATION WITH EMBEDDED FLOATING BODY MEMORY CELL USING A HIGH-K DUAL METAL GATE - Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed. | 01-15-2009 |
| 20090146208 | Independently controlled, double gate nanowire memory cell with self-aligned contacts - A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used. | 06-11-2009 |
| 20090170279 | METHOD OF PREPARING ACTIVE SILICON REGIONS FOR CMOS OR OTHER DEVICES - A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate ( | 07-02-2009 |
| 20090267153 | Localized Spacer For A Multi-Gate Transistor - In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed. | 10-29-2009 |
| 20100072533 | ASYMMETRIC CHANNEL DOPING FOR IMPROVED MEMORY OPERATION FOR FLOATING BODY CELL (FBC) MEMORY - An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage. | 03-25-2010 |
| 20100155880 | Back gate doping for SOI substrates - A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×10 | 06-24-2010 |
