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Balster
Emmanuel Balster, Holte DK
| Patent application number | Description | Published |
|---|---|---|
| 20110191028 | MEASUREMENT DEVICES WITH MEMORY TAGS AND METHODS THEREOF - A downhole measurement device includes one or more sensors configured to measure a parameter in a well; a plurality of memory tags for storing measurement data from the one or more sensors; and an ejection module configured to release one of the plurality of memory tags upon a predetermined condition. A method for monitoring a well includes deploying of a measurement device having one or more sensors and a plurality of memory tags into a wellbore; obtaining measurement data of the parameter using the one or more sensors; writing the measurement data to one of the plurality of memory tags; releasing the memory tag having the measurement data; allowing the memory tag having the measurement data to be carried by a flow in the wellbore uphole; reading the measurement data from the memory tag having the measurement data at a location remote from the downhole measurement device. | 08-04-2011 |
Eric Balster, Kettering, OH US
| Patent application number | Description | Published |
|---|---|---|
| 20100014586 | FRAME DECIMATION THROUGH FRAME SIMPLICATION - System and method of providing improved signal compression using frame decimation through frame simplification and generating an encoded bitstream of video frames therefrom are disclosed. The encoding method comprises zeroing a difference frame generated by an encoder by using a feedback loop that injects a reconstructed frame, generated by the encoder of the difference frame, as a next frame of the video frames to be processed by the encoder. The encoding system comprises an input configured to provide a stream of video frames; a first process configured to generate a difference frame, and a second process configured to generate a reconstructed frame. A feedback loop of the system is configured to inject a generated reconstructed frame from the second process of a generated difference frame from the first process as a next frame of the video frames in the stream to be processed into the encoded bitstream by the encoding system. | 01-21-2010 |
Eric Balster, Dayton, OH US
| Patent application number | Description | Published |
|---|---|---|
| 20120033880 | IMAGE PROCESSING SYSTEMS EMPLOYING IMAGE COMPRESSION AND ACCELERATED IMAGE DECOMPRESSION - A system for processing an image includes a non-transitory memory component storing a set of executable instructions, and a scalable tile processing device. The executable instructions cause the system to receive image data, partition the image data into tiles, transmit a tile to the scalable tile processing device, receive an encoded bit stream corresponding to the transmitted tile from the tile processing device, output compressed image data including the encoded bit stream, receive the compressed image data, decode the compressed image data to generate a plurality of decoded code blocks, and output decompressed image data including the plurality of decoded code blocks. The scalable tile processing device receives the tile including tile image data, wavelet transforms, quantizes, segments, and encodes the tile image data to generate a plurality of encoded code blocks, and transmits an encoded bit stream including the plurality of encoded code blocks to the system. | 02-09-2012 |
| 20120033881 | IMAGE PROCESSING SYSTEMS EMPLOYING IMAGE COMPRESSION AND ACCELERATED DECOMPRESSION - A system for processing an image includes a non-transitory memory component storing a set of executable instructions, and a scalable tile processing device. The executable instructions cause the system to receive image data, partition the image data into tiles, transmit a tile to the scalable tile processing device, receive an encoded bit stream corresponding to the transmitted tile from the tile processing device, output compressed image data including the encoded bit stream, receive the compressed image data, decode the compressed image data to generate a plurality of decoded code blocks, and output decompressed image data including the plurality of decoded code blocks. The scalable tile processing device receives the tile including tile image data, wavelet transforms, quantizes, segments, and encodes the tile image data to generate a plurality of encoded code blocks, and transmits an encoded bit stream including the plurality of encoded code blocks to the system. | 02-09-2012 |
| 20120033886 | IMAGE PROCESSING SYSTEMS EMPLOYING IMAGE COMPRESSION - A system for processing an image includes a an image data input port, a compressed image data output port or a compressed image data storage node, a non-transitory memory component storing a set of executable instructions, and a scalable tile processing device. The executable instructions cause the system to receive image data, partition the image data into tiles, transmit a tile to the scalable tile processing device, receive an encoded bit stream corresponding to the transmitted tile from the tile processing device, and output compressed image data including the encoded bit stream. The scalable tile processing device receives the tile including tile image data, wavelet transforms, quantizes, segments, and encodes the tile image data to generate a plurality of encoded code blocks, and transmits an encoded bit stream including the plurality of encoded code blocks to the system. | 02-09-2012 |
Jörg Henning Balster, Enschede NL
| Patent application number | Description | Published |
|---|---|---|
| 20100065490 | ION-PERMEABLE MEMBRANE AND THE PRODUCTION THEREOF - A method for producing an ion-permeable membrane which has at least one profiled surface includes contacting a shaping element with an uncured polymer film which contains at least one polymer, impressing the shaping element onto the polymer film and generating a regular pattern of identically or differently structured elevations and/or recesses on the polymer film. | 03-18-2010 |
Jörg Henning Balster, Enschede NL
| Patent application number | Description | Published |
|---|---|---|
| 20100065490 | ION-PERMEABLE MEMBRANE AND THE PRODUCTION THEREOF - A method for producing an ion-permeable membrane which has at least one profiled surface includes contacting a shaping element with an uncured polymer film which contains at least one polymer, impressing the shaping element onto the polymer film and generating a regular pattern of identically or differently structured elevations and/or recesses on the polymer film. | 03-18-2010 |
Scott Balster, Munchen DE
| Patent application number | Description | Published |
|---|---|---|
| 20090130805 | ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS - The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer ( | 05-21-2009 |
Scott Balster, Dallas, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090127630 | Method for Fabricating Isolated Integrated Semiconductor Structures - An integrated semiconductor structure and a method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. | 05-21-2009 |
| 20110111553 | ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS - The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer ( | 05-12-2011 |
Scott Balster, Munich DE
| Patent application number | Description | Published |
|---|---|---|
| 20080265368 | Integrated Stacked Capacitor and Method of Fabricating Same - An integrated stacked capacitor comprises a first capacitor film ( | 10-30-2008 |
Scott G. Balster, Munich DE
| Patent application number | Description | Published |
|---|---|---|
| 20100279481 | CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS - An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors ( | 11-04-2010 |
Scott Gerard Balster, Dallas, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100032804 | HIGH VOLTAGE BIPOLAR TRANSISTOR AND METHOD OF FABRICATION - High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed. | 02-11-2010 |
| 20100308416 | Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection - An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit. | 12-09-2010 |