| Patent application number | Description | Published |
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| 20090013218 | DATALOG MANAGEMENT IN SEMICONDUCTOR TESTING - Methods, systems and modules for datalog management. In one embodiment, the logging of data is allowed to at least occasionally occur while the handling equipment is preparing device(s) for testing. Additionally or alternatively, in one embodiment with a plurality of test site controllers, after testing has been completed at all test site(s) associated with a particular test site controller the logging of data relating to that test site controller is allowed to at least occasionally occur while testing is continuing at test site(s) associated with other test site controller(s). | 01-08-2009 |
| 20090112501 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted. | 04-30-2009 |
| 20090115445 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted. | 05-07-2009 |
| 20090119048 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted. | 05-07-2009 |
| 20090192754 | SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner. | 07-30-2009 |
| 20090265300 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING A TESTING SCENARIO LANGUAGE - Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs. | 10-22-2009 |
| 20100161276 | System and Methods for Parametric Test Time Reduction - A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification which defines a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method comprising, for at least one parametric test, computing an estimated maximum test range, at a given confidence level, on a validation set comprising a subset of the population of semiconductor devices, the estimated maximum test range comprising the range of values into which all results from performing the test on the set will statistically fall at the given confidence level, the validation set defining a complementary set including all semiconductors included in the population and not included in the validation set; and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range. | 06-24-2010 |
