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| 20110171719 | Prevention and Remediation of Petroleum Reservoir Souring and Corrosion by Treatment with Virulent Bacteriophage - Petroleum reservoir souring, caused by microbially induced production of hydrogen sulfide and other sulfur compounds, and the attendant corrosion are remediated by isolating bacteriophage(s) specific for the problematic bacteria (target bacteria) and adding an effective amount of such bacteriophage(s) to water introduced into or resident in the reservoir to kill at least some of the target bacteria. Suitable virulent bacteriophage(s) may be indigenous to the water, located in surrounding areas, or taken from a known banked stock. Means of concentrating solutions of bacteriophage(s) are also disclosed. | 07-14-2011 |
| 20120040329 | Process For Continuous Production Of Bacteriophage - As bacteriophage use in industrial application grows there is a need for commercial quantities of identified bacteriophage. This invention discloses a continuous flow bacteriophage proliferation process that can provide commercial quantities of desired bacteriophage in concentrations suitable for industrial use. Host bacteria and virulent bacteriophage are fed into a reactor vessel where the phage attach to, infect and lyse the host bacteria providing multiple replications of it and coincidentally concentrating the phage. | 02-16-2012 |
| 20120040439 | Use of Prokaryote Viruses to Remediate Bio-Fouling - This invention provides a process for control in oil and gas wells and related facilities of prokaryote caused souring, fouling and corrosion by reduction of problematic prokaryotes with naturally occurring lysing organisms, particularly sulfate-reducing prokaryotes by proliferating suitable virulent lysing organisms under conditions in which problematic prokaryotes thrive, including in a gas production wellbore. The process provides in situ proliferation of virulent lysing organism in a wellbore by providing both virulent lysing organisms and their host prokaryotes to selectively grow an effective control amount and concentrations of lysing organisms in a well formation. | 02-16-2012 |
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| 20080286933 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 11-20-2008 |
| 20090096031 | DIFFERENTIAL POLY DOPING AND CIRCUITS THEREFROM - A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant. | 04-16-2009 |
| 20090098694 | CD GATE BIAS REDUCTION AND DIFFERENTIAL N+ POLY DOPING FOR CMOS CIRCUITS - A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices. | 04-16-2009 |
| 20100327335 | METHOD OF BUILDING COMPENSATED ISOLATED P-WELL DEVICES - Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow. | 12-30-2010 |
| 20100327361 | LOW COST SYMMETRIC TRANSISTORS - An integrated circuit is disclosed containing two types of MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. | 12-30-2010 |
| 20100327374 | LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS - An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed. | 12-30-2010 |
| 20110133880 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 06-09-2011 |
| 20110156144 | Compensated Isolated P-WELL DENMOS Devices - An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. | 06-30-2011 |
| 20110248347 | LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS - An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed. | 10-13-2011 |
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| 20120043612 | Device Layout in Integrated Circuits to Reduce Stress from Embedded Silicon-Germanium - An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated. | 02-23-2012 |
| 20120074973 | ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS - An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters. | 03-29-2012 |
| 20120074980 | SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES - An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters. | 03-29-2012 |
| 20120078604 | METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN CMOS PROCESSES THROUGH DESIGN RULE RESTRICTIONS - Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations. | 03-29-2012 |
| 20120091531 | Flexible Integration of Logic Blocks with Transistors of Different Threshold Voltages - An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions. | 04-19-2012 |
