Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Balch, NY
Bruce Balch, Saranac, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090295402 | VOLTAGE ISLAND PERFORMANCE/LEAKAGE SCREEN MONITOR FOR IP CHARACTERIZATION - A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island. | 12-03-2009 |
| 20100174503 | Monitoring NFET/PFET Skew in Complementary Metal Oxide Semiconductor Devices - An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance. | 07-08-2010 |
| 20100244132 | Methods for Normalizing Strain in Semiconductor Devices and Strain Normalized Semiconductor Devices - A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor. | 09-30-2010 |
Bruce W. Balch, Saranac, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090068772 | ACROSS RETICLE VARIATION MODELING AND RELATED RETICLE - Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips. | 03-12-2009 |
Ernest Wayne Balch, Ballston Spa, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090199392 | ULTRASOUND TRANSDUCER PROBES AND SYSTEM AND METHOD OF MANUFACTURE - A method for fabricating an ultrasound transducer structure is disclosed. The method includes performing the steps of forming a functional layer, including an ultrasound transducer material and a photopolymer, and exposing a plurality of selected regions of the functional layer to a programmable light pattern to cure the selected regions of the functional layer to form polymerized ultrasound transducer material regions, repeatedly. The method further includes selectively removing unexposed regions of the functional layer to obtain a green component, and sintering the green component to obtain the sensing structure. A system for making at least one piezoelectric element is also disclosed. | 08-13-2009 |
| 20120009733 | POWER SEMICONDUCTOR MODULE AND FABRICATION METHOD - A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor. | 01-12-2012 |
Gary Stephen Balch, Ballston Spa, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20120287556 | AMORPHOUS POLYCARBONATE FILMS FOR CAPACITORS, METHODS OF MANUFACTURE, AND ARTICLES MANUFACTURED THEREFROM - A uniaxially-stretched, extruded film comprising a polycarbonate, wherein the extruded film has at least one wrinkle-free region having a first surface and a second surface, the at least one extruded wrinkle-free region comprising: an extruded thickness of more than 0 and less than 7 micrometer, and a variation of the thickness of the film of +/−10% of the thickness of the film, and a surface roughness average that is less than +/−3% of the average thickness of the film as measured by optional profilometery; and further wherein the film has a dielectric constant at 1 kHz and room temperature of at least 2.7; a dissipation factor at 1 kHz and room temperature of 1% or less; and a breakdown strength of at least 300 Volt/micrometer. | 11-15-2012 |
Joleyn Eileen Balch, Schaghticoke, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100108132 | NANO-DEVICES AND METHODS OF MANUFACTURE THEREOF - Disclosed herein is a nanodevice. Disclosed herein too is a method of manufacturing a nanodevice. In one embodiment the nanodevice includes a first substrate; a second substrate; a nanowire; the nanowire contacting the first substrate and the second substrate; the nanowire comprising a metal, a semi-conductor or a combination thereof. | 05-06-2010 |
| 20100147762 | MEMBRANE ASSEMBLIES AND METHODS OF MAKING AND USING THE SAME - A method of making a membrane assembly is provided. The method comprises forming an inorganic membrane layer disposed on a substrate, and forming a plurality of macropores in the substrate at least in part using anodization. Further, a membrane assembly is provided. The membrane assembly comprises a filtering membrane that is coupled to an anodized substrate comprising a plurality of macropores. | 06-17-2010 |
| 20100261338 | Nanostructures, methods of depositing nanostructures and devices incorporating the same - A method for depositing nanowires is disclosed. The method includes depositing multiple nanowires onto a surface of a liquid. The method also includes partially compressing the nanowires. The method also includes dipping a substrate into the liquid. The method further includes pulling the substrate out of the liquid at a controlled speed. The method also includes transferring the nanowires onto the substrate parallel to a direction of the pulling. | 10-14-2010 |