| Patent application number | Description | Published |
|---|
| 20080244282 | Managing Power Allocation To Ethernet Ports In The Absence Of Mutually Exclusive Detection And Powering Cycles In Hardware - A method of allocating power to ports in an Ethernet switch, including: (1) assigning a configuration power to a selected port, wherein the assigned configuration power is less than a power supplied by the selected port to a powered, (2) enabling and powering the selected port in a single indivisible step, (3) determining the power limit of a device coupled to the selected port, (4) comparing the power supplied by the selected port to the device with the configuration power assigned to the selected port, and (5) if the power supplied by the selected port to the device is greater than the configuration power assigned to the selected port, then increasing the configuration power of the selected port to correspond with the power limit of the device. | 10-02-2008 |
| 20090279423 | Recovering from Failures Without Impact on Data Traffic in a Shared Bus Architecture - Methods of detecting and recovering from communication failures within an operating network switching device that is switching packets in a communication network, and associated structures. The communication failures addressed involve communications between the packet processors and a host CPU over a shared communications bus, e.g., PCI bus. The affected packet processor(s)—which may be all or a subset of the packet processors of the network switch—may be recovered without affecting hardware packet forwarding through the affected packet processors. This maximizes the up time of the network switching device. Other packet processor(s), if any, of the network switching device, which are not affected by the communication failure, may continue their normal packet forwarding, i.e., hardware forwarding that does not involve communications with the host CPU as well as forwarding or other operations that do involve communications with the host CPU. | 11-12-2009 |
| Patent application number | Description | Published |
|---|
| 20090282307 | Optimizing test code generation for verification environment - A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets. | 11-12-2009 |
| 20100083195 | CONTROL SIGNAL SOURCE REPLICATION - Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block. | 04-01-2010 |
| 20100217564 | ADVANCED PHYSICAL SIMULATOR - A method of physical simulation of an integrated circuit design comprising the steps of (A) reading design information for an integrated circuit from a computer readable storage medium, (B) reading library information and physical design information from the computer readable storage medium, (C) simulating the integrated circuit design based upon the library information and the physical design information using a computer, where the simulation of the integrated circuit design provides signoff accurate results and (D) determining whether the integrated circuit design meets one or more performance goals based upon results of the simulation of the integrated circuit design. | 08-26-2010 |
| Patent application number | Description | Published |
|---|
| 20090190552 | FLEXIBLE MOBILE IP FOREIGN AGENT ARCHITECTURE FOR ENABLING CONVERGED SERVICES - A method and apparatus for flexible Mobile IP foreign agent architecture for enabling converged services are described herein. According to one embodiment of the invention, a packet is received over a circuit bound with a converged services domain of a network element. The converged services domain enables forwarding of wired and wireless traffic to a plurality of destination network elements. Upon determining that the circuit is capable of carrying Mobile Internet Protocol (IP) packets, the packet is processed according to an entry ma Mobile IP forwarding information base upon determining that the packet has a corresponding entry in the Mobile IP forwarding information base, and the packet is processed according to a different entry in an IP forwarding information base upon determining that the packet does not have an entry in the Mobile IP forwarding information base. Other methods and apparatuses are also described. | 07-30-2009 |
| 20090248708 | Method and Apparatus for Mobility Agent Recovery - Techniques for recovering Mobile Internet Protocol (IP) session(s) of a mobility agent in a Mobile IP network are described herein. In one embodiment of the invention, for each mobility session associated with a mobility agent, the mobility agent distributively backs up mobility agent specific information to the mobility agent peer associated with that mobility session. The mobility agent specific information is not used by the mobility agent peer. Upon the mobility agent inadvertently losing at least one mobility session, the mobility agent recovers the stored mobility agent specific information associated with those sessions from the mobility agent peers respectively associated with those sessions. Other methods and apparatuses are also described. | 10-01-2009 |
| 20110202663 | Method and Apparatus for Mobility Agent Recovery - Techniques for recovering Mobile Internet Protocol (IP) session(s) of a mobility agent in a Mobile IP network are described herein. In one embodiment of the invention, for each mobility session associated with a mobility agent, the mobility agent distributively backs up mobility agent specific information to the mobility agent peer associated with that mobility session. The mobility agent specific information is not used by the mobility agent peer. Upon the mobility agent inadvertently losing at least one mobility session, the mobility agent recovers the stored mobility agent specific information associated with those sessions from the mobility agent peers respectively associated with those sessions. Other methods and apparatuses are also described. | 08-18-2011 |
| 20110202664 | Method and Apparatus for Mobility Agent Recovery - Techniques for recovering Mobile Internet Protocol (IP) session(s) of a mobility agent in a Mobile IP network are described herein. In one embodiment of the invention, for each mobility session associated with a mobility agent, the mobility agent distributively backs up mobility agent specific information to the mobility agent peer associated with that mobility session. The mobility agent specific information is not used by the mobility agent peer. Upon the mobility agent inadvertently losing at least one mobility session, the mobility agent recovers the stored mobility agent specific information associated with those sessions from the mobility agent peers respectively associated with those sessions. Other methods and apparatuses are also described. | 08-18-2011 |
| 20110202671 | Method and Apparatus for Mobility Agent Recovery - Techniques for recovering Mobile Internet Protocol (IP) session(s) of a mobility agent in a Mobile IP network are described herein. In one embodiment of the invention, for each mobility session associated with a mobility agent, the mobility agent distributively backs up mobility agent specific information to the mobility agent peer associated with that mobility session. The mobility agent specific information is not used by the mobility agent peer. Upon the mobility agent inadvertently losing at least one mobility session, the mobility agent recovers the stored mobility agent specific information associated with those sessions from the mobility agent peers respectively associated with those sessions. Other methods and apparatuses are also described. | 08-18-2011 |
| 20110305235 | FLEXIBLE MOBILE IP FOREIGN AGENT ARCHITECTURE FOR ENABLING CONVERGED SERVICES - A method and apparatus for flexible Mobile IP foreign agent architecture for enabling converged services are described herein. According to one embodiment of the invention, a packet is received over a circuit bound with a converged services domain of a network element. The converged services domain enables forwarding of wired and wireless traffic to a plurality of destination network elements. Upon determining that the circuit is capable of carrying Mobile Internet Protocol (IP) packets, the packet is processed according to an entry in a Mobile IP forwarding information base upon determining that the packet has a corresponding entry in the Mobile IP forwarding information base, and the packet is processed according to a different entry in an IP forwarding information base upon determining that the packet does not have an entry in the Mobile IP forwarding information base. Other methods and apparatuses are also described. | 12-15-2011 |
| Patent application number | Description | Published |
|---|
| 20090106118 | PAYMENT USING FUNDS PUSHING - Apparatus, systems, and methods may operate to present, via a networked client coupled to a first financial entity, a graphical user interface including an account associated with a first party, an amount to be paid, and an email address associated with a second party. Further activities may include receiving an indication from the graphical user interface to transfer, via a selected payment processor, the amount to be paid from the account associated with the first party and held by the first financial entity to an account linked to the email address. The amount to be paid may then be pushed from the account held by the first financial entity directly to the selected payment processor. Additional apparatus, systems, and methods are disclosed. | 04-23-2009 |
| 20090106150 | UNIFIED IDENTITY VERIFICATION - Apparatus, systems, and methods are disclosed that operate to register one time, at a financial entity, information comprising an identity uniquely associated with an individual having a financial account held by the financial entity. Additional actions include receiving a request at the financial entity from a requesting party to authenticate a customer purporting to be the individual, authenticating, by the financial entity, the customer as the individual by matching a token presented by the customer to the identity uniquely associated with the individual, and providing to the requesting party a previously-authorized portion of a profile associated with the individual. Additional apparatus, systems, and methods are disclosed. | 04-23-2009 |
| Patent application number | Description | Published |
|---|
| 20110219183 | SUB-AREA FCID ALLOCATION SCHEME - Certain embodiments of the present disclosure generally relate to allocating a sub-area of Fibre Channel addresses (FCIDs) to a device. A range of addresses may be assigned to the device using a mask address, where the most significant bits represent a mask and the least significant bits represent a sub-range of FCIDs available to be assigned to the device. Therefore, routing information may be stored efficiently in a Ternary Content Addressable Memory (TCAM) by storing a single entry in the TCAM for each sub-area of FCIDs allocated to a device, instead of storing an entry for each FCID. The single entry may indicate the mask address and the width of the mask. | 09-08-2011 |
| 20110228670 | N_Port ID Virtualization node redundancy - In one embodiment, a method includes establishing a link between two N_Port Identifier Virtualization (NPIV) switches, the link having a high cost assigned thereto. The NPIV switches are in communication with a plurality of hosts through an N_Port Virtualization (NPV) device. The method further includes receiving at a first of the NPIV switches, an indication of a failure at a second of the NPIV switches, receiving data at the first NPIV switch, the data destined for one of the hosts associated with a domain of the second NPIV switch, and forwarding the data to the NPV device for delivery to the host, wherein a Fibre Channel Identifier (FCID) of the host is the same before and after the failure at the second NPIV switch. An apparatus is also disclosed. | 09-22-2011 |
| 20110273990 | Per-graph link cost assignment in layer 2 multipath networks - In one embodiment, a method includes assigning at a switch in a layer 2 multipath network, costs to a link in the network, each of the link costs associated with a different graph for forwarding traffic in the network, transmitting the link costs to other switches in the layer | 11-10-2011 |
| 20120027017 | MULTI-DESTINATION FORWARDING IN NETWORK CLOUDS WHICH INCLUDE EMULATED SWITCHES - Techniques are described which facilitate multi-destination forwarding in a Layer 2 Multipath (L2MP) network which includes an emulated switch. The emulated switch may correspond to two or more underlying peer link switches in the L2MP network, in which each of the peer link switches is linked to a Classical Ethernet (CE) switch over a virtual port channel (vPC). Traffic received by one of the peer link switches over the vPC is automatically forwarded to the other peer link switch (or switches). Multi-destination frames originating from the L2MP network addressed to hosts within the CE network are sent over only one of the peer link switches. | 02-02-2012 |
| Patent application number | Description | Published |
|---|
| 20080265935 | INTEGRATED MULTI-FUNCTION ANALOG CIRCUIT INCLUDING VOLTAGE, CURRENT, AND TEMPERATURE MONITOR AND GATE-DRIVER CIRCUIT BLOCKS - An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad. | 10-30-2008 |
| 20080272803 | SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS - An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality of outputs, the programmable logic block, the analog circuit block, and the analog-to-digital converter. At least one of the inputs may be programmably configured as one of a digital input programmably coupleable to elements in the programmable logic block or as an analog input to an analog circuit in the analog circuit block. | 11-06-2008 |
| 20080303547 | PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL - A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log. | 12-11-2008 |
| 20090128186 | PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL - A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads. | 05-21-2009 |
| 20090292937 | PROGRAMMABLE SYSTEM ON A CHIP - A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another. | 11-26-2009 |
| 20100001760 | PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL - A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads. | 01-07-2010 |
| Patent application number | Description | Published |
|---|
| 20110246653 | EFFICIENT PROVISIONING OF RESOURCES IN PUBLIC INFRASTRUCTURE FOR ELECTRONIC DESIGN AUTOMATION (EDA) TASKS - Provisioning resources in public cloud infrastructure to perform at least part of electronic design automation (EDA) tasks on the public cloud infrastructure. Performance metrics of servers in the public cloud infrastructure and performance history of a user's past EDA tasks are maintained to estimate operation parameters such as runtime of a new EDA task. Based on the estimation, a user can provision appropriate types and amounts of resources in the public cloud infrastructure in a cost-efficient manner. Also, a plurality of EDA tasks are assigned to computing resources in a manner that minimizes the overall cost for performing the EDA tasks. | 10-06-2011 |
| 20110301907 | Accelerating Automatic Test Pattern Generation in a Multi-Core Computing Environment via Speculatively Scheduled Sequential Multi-Level Parameter Value Optimization - Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel runs to parallelize sequential execution, speculative software execution to explore possible parameter sets, and terminate/prune runs when the optimum parameter value is found at a previous level. The present invention evaluates the design prior to the implementation of the compression IP so that it can define the configuration of DFT and ATPG to maximize the results of compression as measured by test data volume and test application time. | 12-08-2011 |
| 20120084847 | Secure Provisioning of Resources in Cloud Infrastructure - Provisioning resources in public cloud infrastructure to perform at least part of electronic design automation (EDA) tasks on the public cloud infrastructure. The provisioning of resources is handled by a cloud provisioning system that is generally operated and maintained by an EDA tool developer using a provisioning credential. After the resources are provisioned, the cloud provisioning system places user key on the provisioned resources. Once the user key is placed on the provisioned resources, the cloud provisioning system has only limited access or no access to the provisioned resources. Instead, a user client device takes over the control of the provisioned resources by using a user's access credential. The provisioning credential is retained by the EDA tool developer and is not released to the user. Similarly, the access credential is retained by the user and not released to the EDA tool developer. In this way, the EDA tool developer can retain control of the resources deployed for the EDA tasks while ensuring that the user's information associated with the EDA tasks is secure. | 04-05-2012 |
| Patent application number | Description | Published |
|---|
| 20090089326 | METHOD AND APPARATUS FOR PROVIDING MULTIMEDIA CONTENT OPTIMIZATION - Methods, system and computer readable medium for detecting duplicate content in a pair of media files prior to publication on a webpage include generating fingerprints for the contents of each of the pair of media files. The fingerprints of one of the pair of media file are then compared with the fingerprints of another of the pair of media files to compute a similarity score. The similarity score is compared against an established threshold. If the similarity score exceeds the established threshold, it is determined that the two media files are substantial duplicate of one another. | 04-02-2009 |
| 20090119291 | MICROHUBS AND ITS APPLICATIONS - A system and method of crawling at least one website comprising at least one URL includes maintaining a lookup structure comprising all of the URLs known to be on a website; calculating a hub score for each webpage of the website to be recrawled, wherein the hub score measures how likely the to be recrawled webpage includes links to fresh content published on the website; sorting all the to be recrawled pages by their hub scores; and crawling the to be recrawled pages in order from highest hub scores to lowest hub scores. The calculating comprises computing a first value equaling a percentage of a number of new relative URLs on the to be recrawled page; computing a second value equaling a percentage of a previous hub score of the to be recrawled page; and computing the hub score as a sum of the first and the second values. | 05-07-2009 |
| 20090150456 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DISASTER RECOVERY PLANNING - Formulating an integrated disaster recovery (DR) plan based upon a plurality of DR requirements for an application by receiving a first set of inputs identifying one or more entity types for which the plan is to be formulated, such as an enterprise, one or more sites of the enterprise, the application, or a particular data type for the application. At least one data container representing a subset of data for an application is identified. A second set of inputs is received identifying at least one disaster type for which the plan is to be formulated. A third set of inputs is received identifying a DR requirement for the application as a category of DR Quality of Service (QoS) class to be applied to the disaster type. A composition model is generated specifying one or more respective DR QoS parameters as a function of a corresponding set of one or more QoS parameters representative of a replication technology solution. The replication technology solution encompasses a plurality of storage stack levels. A solution template library is generated for mapping the application to each of a plurality of candidate replication technology solutions. The template library is used to select a DR plan in the form of a replication technology solution for the application. | 06-11-2009 |
| 20090150712 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DISASTER RECOVERY PLANNING - Formulating an integrated disaster recovery (DR) plan based upon a plurality of DR requirements for an application by receiving a first set of inputs identifying one or more entity types for which the plan is to be formulated, such as an enterprise, one or more sites of the enterprise, the application, or a particular data type for the application. At least one data container representing a subset of data for an application is identified. A second set of inputs is received identifying at least one disaster type for which the plan is to be formulated. A third set of inputs is received identifying a DR requirement for the application as a category of DR Quality of Service (QoS) class to be applied to the disaster type. A composition model is generated specifying one or more respective DR QoS parameters as a function of a corresponding set of one or more QoS parameters representative of a replication technology solution. The replication technology solution encompasses a plurality of storage stack levels. A solution template library is generated for mapping the application to each of a plurality of candidate replication technology solutions. The template library is used to select a DR plan in the form of a replication technology solution for the application. | 06-11-2009 |
| Patent application number | Description | Published |
|---|
| 20090123374 | METHODS FOR DETERMINING CANCER RESISTANCE TO HISTONE DEACETYLASE INHIBITORS - Described herein are methods and compositions for determining whether a particular cancer is resistant to or susceptible to a histone deacetylase inhibitor or to histone deacetylase inhibitors. The methods include analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are methods and compositions for increasing the likelihood of a therapeutically effective treatment in a patient, comprising an analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are isolated populations of nucleic acids derived from a cancer sensitive to or resistant to a histone deacetylase inhibitor. Further described are kits and indications that are optionally used in conjunction with the aforementioned methods and compositions. | 05-14-2009 |
| 20100285516 | CALCIUM FLUX AS A PHARMACOEFFICACY BIOMARKER FOR INHIBITORS OF HISTONE DEACETYLASE - Described herein are methods for using calcium flux as a biomarker to select and predict patients likely to respond to an apoptotic agent as therapy. Further described herein is a method of using calcium flux as a clinical biomarker to determine whether a tumor is sensitive to an HDAC inhibitor. | 11-11-2010 |
| 20110053164 | METHODS FOR DETERMINING CANCER RESISTANCE TO HISTONE DEACETYLASE INHIBITORS - Described herein are methods and compositions for determining whether a particular cancer is resistant to or susceptible to a histone deacetylase inhibitor or to histone deacetylase inhibitors. The methods include analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are methods and compositions for increasing the likelihood of a therapeutically effective treatment in a patient, comprising an analysis of the expression levels of at least four biomarker genes associated with response to a histone deacetylase inhibitor. Also described herein are isolated populations of nucleic acids derived from a cancer sensitive to or resistant to a histone deacetylase inhibitor. Further described are kits and indications that are optionally used in conjunction with the aforementioned methods and compositions. | 03-03-2011 |
| 20110081409 | SELECTIVE INHIBITORS OF HISTONE DEACETYLASE - Described herein are compounds and pharmaceutical compositions containing such compounds, which inhibit the activity of histone deacetylase 8 (HDAC8). Also described herein are methods of using such HDAC8 inhibitors, alone and in combination with other compounds, for treating diseases or conditions that would benefit from inhibition of HDAC8 activity. | 04-07-2011 |
| 20110150825 | USES OF SELECTIVE INHIBITORS OF HDAC8 FOR TREATMENT OF INFLAMMATORY CONDITIONS - Described herein are methods for treating a subject suffering from an inflammatory, autoimmune, or heteroimmune condition by administering to the subject a pharmaceutical composition containing a therapeutically effective amount of a compound that is a selective inhibitor of histone deacetylase 8. Also described herein are methods for decreasing secretion of pro-inflammatory cytokines by administering an HDAC8-selective inhibitor compound. Further described herein are methods for predicting responsiveness to treatments for inflammatory conditions. Methods for predicting efficacy of treatments for inflammatory conditions are also described. | 06-23-2011 |
| 20110311624 | FORMULATIONS OF HISTONE DEACETYLASE INHIBITOR AND USES THEREOF - Dosing regimens, methods of treatment, controlled release formulations, and combination therapies that include an HDAC inhibitor, or a pharmaceutically acceptable salt thereof, are described. | 12-22-2011 |
| Patent application number | Description | Published |
|---|
| 20090050984 | MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins extending from the impurity-doped region are fabricated and a metal silicide layer is formed on the contact fins. A contact to at least a portion of the metal silicide layer on at least one of the contact fins is fabricated. | 02-26-2009 |
| 20090259453 | Method of modeling SRAM cell - A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The present methodology streamlines the modeling process by modeling in order the pull up, pass gate and pull down transistors so as to minimize the number of transistor modeling iterations needed, and by focusing on the specific areas of transistor operation to achieve the desired level of operational accuracy. Variations to the model are provided, mimicking variations in data from actual devices, and yield based on failure estimation is measured using the model and its variations. | 10-15-2009 |
| 20110233627 | MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. With the gate stack serving as a mask, impurity dopants are implanted into a semiconductor material having a first surface and disposed proximate to the gate stack. A trench is etched into the semiconductor material such that the semiconductor material has a trench surface within the trench. Further, a metal silicide layer is formed on the first surface of the semiconductor material and on the trench surface. Also, a contact to at least a portion of the metal silicide layer on the first surface and at least a portion of the metal silicide layer on the trench surface is fabricated. | 09-29-2011 |
