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Bakker, CA
Alice Bakker, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080281076 | IL-6 binding proteins - Polypeptides comprising monomer domains that bind to IL-6, or portions thereof, are provided. | 11-13-2008 |
| 20090305962 | IL-6 binding proteins - Polypeptides comprising monomer domains that bind to IL-6, or portions thereof, are provided. | 12-10-2009 |
| 20100292167 | C-MET KINASE BINDING PROTEINS - Polypeptides comprising monomer domains that bind to c-MET, or portions thereof, are provided. | 11-18-2010 |
| 20110150901 | BINDING PROTEINS THAT BIND TO HUMAN FGFR1C, HUMAN BETA-KLOTHO AND BOTH HUMAN FGFR1C AND HUMAN BETA-KLOTHO - Binding proteins that specifically bind to β-Klotho or portions thereof, FGFR1c or portions thereof, or both FGFR1c and β-Klotho, and optionally other proteins as well are provided. Coding sequences, methods of treatment and pharmaceutical compositions are also provided. | 06-23-2011 |
Anthonius Bakker, Morgan Hill, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080284403 | High-side current sense circuit with common-mode voltage reduction - A high-side current sense circuit comprises a sense resistance R | 11-20-2008 |
| 20080309300 | Digital current share bus interface - A digital current share bus interface connects to a power module which provides a signal representative of its output current, and adjusts the module's output current in response to a control signal received from the interface. A data formatting module receives the output current signal and generates a digital word that varies with the current; the bits of the word are coupled to a current share bus. A comparator module receives digital words conveyed via the bus and generated by the data formatting module at respective inputs, and provides the control signal to the power module so as to adjust its output current to match the current value represented by the digital word on the bus. In a typical implementation, multiple power modules are coupled to the current share bus via respective interfaces, with the output currents of all the power modules connected in parallel. | 12-18-2008 |
| 20110006763 | HALL EFFECT CURRENT SENSOR SYSTEM AND ASSOCIATED FLIP-CHIP PACKAGING - A Hall effect current sensor system comprises a semiconductor die, a lead frame structure and a PCB board. The semiconductor die has Hall effect sensor fabricated on it. The lead frame structure comprises at least two extended electrical leads. A conductor bar is printed on the PCB board. The two extended electrical leads and the conductor bar form a closed current path for generating a direct magnetic field. When the Hall effect sensor is inside the closed loop of the current path, current information can be obtained. | 01-13-2011 |
| 20110187416 | SMART DRIVER FOR FLYBACK CONVERTERS - The present invention discloses a smart driver used in flyback converters adopting a transconductance amplifier to turn on a synchronous rectifier FET, and a comparator to quickly turn off the synchronous rectifier FET. | 08-04-2011 |
Antonius Bakker, Morgan Hill, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120062159 | DC BRUSHLESS MOTOR SYSTEM AND THE METHOD THEREOF - A DC brushless motor system is disclosed. When a rotor of the DC brushless motor is close to an aligned position, there will be current spike in the coil and voltage spike in an input capacitor. By decreasing the peak current limit of the current in the coil when the rotor is close to the aligned position, the current spike and the voltage spike are reduced. | 03-15-2012 |
Arnold Hendrik Bakker, Berkeley, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110269155 | Detecting Antigen Responsive Cells in a Sample - The present invention relates to methods for detecting antigen responsive cells in a sample using multidimensional labeled antigen presenting compounds, such as antigen-major histocompatibility complexes (NHC). Further, the present invention relates to the use of the present multidimensional labeled antigen presenting compounds, such as antigen-major histocompatibility complexes (MHC), for detecting antigen responsive cells in a sample, preferably a single sample, such as a blood sample. The present method allows high-throughput analysis of specific antigen responsive cells, such as T- and B-cells, thereby providing, for example, high-throughput methods for monitoring of diseases or conditions and the development of immunotherapeutics, vaccines, or the identification epitopes or immunogenic amino acid sequences. | 11-03-2011 |
Dave Bakker, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080264905 | METHODS AND SYSTEMS FOR MEASURING A CHARACTERISTIC OF A SUBSTRATE OR PREPARING A SUBSTRATE FOR ANALYSIS - Methods and systems for measuring a characteristic of a substrate or preparing a substrate for analysis are provided. One method for measuring a characteristic of a substrate includes removing a portion of a feature on the substrate using an electron beam to expose a cross-sectional profile of a remaining portion of the feature. The feature may be a photoresist feature. The method also includes measuring a characteristic of the cross-sectional profile. A method for preparing a substrate for analysis includes removing a portion of a material on the substrate proximate to a defect using chemical etching in combination with an electron beam. The defect may be a subsurface defect or a partially subsurface defect. Another method for preparing a substrate for analysis includes removing a portion of a material on a substrate proximate to a defect using chemical etching in combination with an electron beam and a light beam. | 10-30-2008 |
Greg Bakker, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090292937 | PROGRAMMABLE SYSTEM ON A CHIP - A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another. | 11-26-2009 |
Gregory W. Bakker, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090051050 | CORNER I/O PAD DENSITY - An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of I/O cells having an I/O pad disposed thereon and spaced at a first distance from the periphery of the die. A second group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the second group of I/O cells having an I/O pad disposed thereon and spaced at a distance from the periphery of the die more than the first distance, the distance increasing as a function of the proximity of each I/O cell to a corner of the die. | 02-26-2009 |
| 20100156459 | PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE - A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal. | 06-24-2010 |