Patent application number | Description | Published |
20130114652 | CREST FACTOR REDUCTION (CFR) USING ASYMMETRICAL PULSES - Crest factor reduction (CFR) techniques are provided using asymmetrical pulses. A crest factor reduction method comprises obtaining one or more data samples; detecting at least one peak in the one or more data samples; performing peak cancellation on the at least one detected peak by applying an asymmetric cancellation pulse to the at least one detected peak: and providing processed versions of the one or more data samples. The asymmetric cancellation pulse is generated, for example, by a minimum phase filter and has a substantially minimum group delay. New peaks associated with peak re-growth are introduced substantially only to the one side of the asymmetric cancellation pulse. The process can optionally rewind by an amount greater than or substantially equal to a group delay of the asymmetric cancellation pulse to address the limited number of pre-cursors that may be present in the asymmetric cancellation pulse. | 05-09-2013 |
20130114761 | MULTI-STAGE CREST FACTOR REDUCTION (CFR) FOR MULTI-CHANNEL MULTI-STANDARD RADIO - Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of the first and second individual crest factor reduction blocks to generate an aggregated output; and applying the aggregated output to a composite crest factor reduction block. The individual crest factor reduction blocks can be implemented using a sampling rate appropriate for the corresponding technology type. The composite crest factor reduction block operates at a higher sampling rate than the individual crest factor reduction blocks. | 05-09-2013 |
20130114762 | RECURSIVE DIGITAL PRE-DISTORTION (DPD) - Recursive digital pre-distortion (DPD) techniques are provided. Digital pre-distortion is performed by applying a signal to a recursive system to generate a state vector; providing the state vector as a feedback value to the recursive non-linear system; and applying the state vector to a second function to generate an output signal, wherein at least one of the recursive system and the second function comprise a non-linear function. The recursive non-linear system can be initialized to a known initial value. The recursive system is defined by a system of non-linear differential equations. | 05-09-2013 |
20130117342 | COMBINED RF EQUALIZER AND I/Q IMBALANCE CORRECTION - Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal. | 05-09-2013 |
20130336144 | RECEIVER AND METHOD FOR ESTIMATING A PLURALITY OF ESTIMATED TRANSFER FUNCTIONS CORRESPONDING TO WIRELESS CHANNELS IN A MULTIPLE-INPUT SYSTEM - In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions. | 12-19-2013 |
20140064417 | Direct Digital Synthesis Of Signals Using Maximum Likelihood Bit-Stream Encoding - Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal. | 03-06-2014 |
20140072073 | BLOCK-BASED CREST FACTOR REDUCTION (CFR) - Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks. | 03-13-2014 |
20140075162 | DIGITAL PROCESSOR HAVING INSTRUCTION SET WITH COMPLEX EXPONENTIAL NON-LINEAR FUNCTION - A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to θ; and computing a fine corrective value using a polynomial approximation. | 03-13-2014 |
20140086356 | Software Digital Front End (SoftDFE) Signal Processing - Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an x | 03-27-2014 |
20140086361 | PROCESSOR HAVING INSTRUCTION SET WITH USER-DEFINED NON-LINEAR FUNCTIONS FOR DIGITAL PRE-DISTORTION (DPD) AND OTHER NON-LINEAR APPLICATIONS - A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software instructions for at least one non-linear function having at least one user-specified parameter, performing the following steps: invoking at least one functional unit that implements the at least one software instruction to apply the non-linear function to the input value, x; and generating an output corresponding to the non-linear function for the input value, x. The user-specified parameter can optionally be loaded from memory into at least one register. | 03-27-2014 |
20140086367 | Maximum Likelihood Bit-Stream Generation and Detection Using M-Algorithm and Infinite Impulse Response Filtering - Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal. | 03-27-2014 |
20140108477 | VECTOR PROCESSOR HAVING INSTRUCTION SET WITH VECTOR CONVOLUTION FUNCTION FOR FIR FILTERING - A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N | 04-17-2014 |
20140119427 | Method and Apparatus for High Density Pulse Density Modulation - A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency. | 05-01-2014 |
20140159991 | SWITCHING POWER AMPLIFIER SYSTEM FOR MULTI-PATH SIGNAL INTERLEAVING - A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal. | 06-12-2014 |
20140177767 | METHOD AND APPARATUS FOR JOINT EQUALIZATION AND DECODING OF MULTIDIMENSIONAL CODES TRANSMITTED OVER MULTIPLE SYMBOL DURATIONS - Techniques are provided for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. A reduced state sequence estimation (RSSE) decoder is provided for a multidimensional code. A multidimensional code symbol comprises a number of symbol components of lower dimensionality. The RSSE decodes comprises at least one branch metric unit that calculates branch metrics for a received signal based on intersymbol interference and intrasymbol interference estimates, the at least one branch metric unit compensating for intrasymbol interference caused by symbol components within a current multidimensional code symbol; and a decision feedback unit that processes survivor symbols to calculate the intersymbol interference estimates for different code states of the multidimensional code and channels used to transmit the multidimensional code. | 06-26-2014 |
20140184323 | Hybrid Digital/Analog Power Amplifier - The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA. | 07-03-2014 |
20140191801 | BICMOS GATE DRIVER FOR CLASS-S RADIO FREQUENCY POWER AMPLIFIER - The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems. | 07-10-2014 |
20140313946 | Non-Linear Interference Cancellation For Wireless Transceivers - Non-linear interference cancellation techniques are provided for wireless transceivers. Non-linear reduction of interference of a transmit signal on a received signal in a transceiver device, comprises applying the transmit signal to a first non-linear system; applying the received signal to a second non-linear system; and subtracting an output of the first non-linear system output from an output of second non-linear system output to produce an interference mitigated received signal. The first non-linear system and/or the second non-linear system can be to implemented using one or more of a Volterra series and a Generalized Memory Polynomial Model. System parameters of the first non-linear system and/or the second non-linear system are adapted to reduce a power of the interference mitigated received signal. | 10-23-2014 |
20140314176 | Non-Linear Modeling of a Physical System Using Two-Dimensional Look-Up Table with Bilinear Interpolation - Methods and apparatus are provided for non-linear modeling of a physical system using two-dimensional look-up tables with bilinear interpolation. A non-linear function is evaluated for a complex input value by obtaining a two-dimensional (2D) look-up table with bilinear interpolation that represents the non-linear function; obtaining four points from the 2D look-up table that are in a vicinity of the complex input value; and generating a complex output value comprised of a bilinear combination of the four points. The non-linear function characterizes, for example, a power amplifier or an inverse of a power amplifier and the 2D look-up tables can be used, for example, to implement digital pre-distortion. The 2D look-up tables with bilinear interpolation can be used in a processor instruction as part of an instruction set of one or more of a scalar processor and a vector processor. | 10-23-2014 |
20140314181 | Non-Linear Modeling of a Physical System Using Look-Up Table with Polynomial Interpolation - Methods and apparatus are provided for non-linear modeling of a physical system using look-up tables with polynomial interpolation. A non-linear function is evaluated for a complex input value by obtaining at least one look-up table with polynomial interpolation that represents the non-linear function, wherein entries in the look-up table comprise polynomial coefficients of at least degree two for different segments of the non-linear function; obtaining a point from the look-up table that is near a magnitude of the complex input value; and generating a complex output value by evaluating the polynomial coefficients at the point to perform a Taylor Series expansion from said point. The non-linear function characterizes, for example, a power amplifier or an inverse of a power amplifier and the look-up tables can be used, for example, to implement digital pre-distortion. The look-up table can be stored in a memory of a digital processor, and the polynomial interpolation can be performed as part of a user-defined non-linear instruction that takes a complex number as an input, x, and computes ƒ(x). | 10-23-2014 |
20140314182 | Modeling of a Target Volterra Series Using an Orthogonal Parallel Wiener Decomposition - Improved techniques are provided for modeling a target Volterra series using an orthogonal parallel Weiner decomposition. A target Volterra Series is modeled by obtaining the target Volterra Series V comprised of a plurality of terms up to degree K; providing a parallel Wiener decomposition representing the target Volterra Series V, wherein the parallel Wiener decomposition is comprised of a plurality of linear filters in series with at least one corresponding static non-linear function, wherein an input signal is applied to the plurality of linear filters and wherein outputs of the non-linear functions are linearly combined to produce an output of the parallel Wiener decomposition; computing a matrix C. for a given degree up to the degree K, wherein a given row of the matrix C corresponds to one of the linear filters and is obtained by enumerating monomial cross-products of coefficients of the corresponding linear filter for the given degree; and determining filter coefficients for at least one of the plurality of linear filters, such that the rows of the matrix C are linearly independent. | 10-23-2014 |
20140316752 | Non-Linear Modeling of a Physical System Using Direct Optimization of Look-Up Table Values - Techniques for non-linear modeling of a physical system are provided using direct optimization of look-up table values. A non-linear system with memory is modeled by obtaining physical data for the non-linear system by applying a set of input samples x(n) to the non-linear system and measuring an output y(n) of the non-linear system; directly computing parameters Φ of a memory model for the non-linear system from the physical data, wherein the memory model comprises one or more look-up tables having linear interpolation and wherein the parameters Φ produce a substantially minimum mean square error; and providing the parameters Φ for storage as entries in the one or more look-up tables. The mean square error can be determined, for example, using one or more of a least squares algorithm, a least mean square algorithm and a recursive least squares algorithm. The look-up tables are optionally used in a processor instruction to implement digital pre-distortion. | 10-23-2014 |
20140317163 | Vector Processor Having Instruction Set With Sliding Window Non-Linear Convolutional Function - A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function. | 10-23-2014 |
20140317376 | Digital Processor Having Instruction Set with Complex Angle Function - A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input; in response to at least one of the complex angle software instructions, performing the following steps: invoking at least one complex angle functional unit that implements the one or more complex angle software instructions to apply the complex angle function to the input value, x; and generating an output corresponding to the complex angle of the input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of the digital processor, wherein the complex angle software instruction is part of an instruction set of the digital signal processor. Multiplication operations optionally employ one or more multipliers of the MAC unit of the digital processor. | 10-23-2014 |