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Ayyapureddi

Sujeet Ayyapureddi, Boise, ID US

Patent application numberDescriptionPublished
20080229008Sharing physical memory locations in memory devices - A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.09-18-2008
20090072855DYNAMICALLY ADJUSTING OPERATION OF A CIRCUIT WITHIN A SEMICONDUCTOR DEVICE - Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a matching circuit including a first plurality of switching devices coupled to each other in parallel and not coupled in parallel to a resistive device, a driver circuit including a plurality of driver devices (the driver circuit adjusted based upon which of the switching devices are enabled), and processing logic that couples to the matching and driver circuits. The processing logic derives a binary value indicative of which of the switching devices are to be enabled, the binary value reflecting one or more process comers associated with the switching devices, and not reflecting one or more process comers associated with the resistive device. The processing logic further maps the binary value to a control value used to adjust the driver circuit.03-19-2009
20090254925SYSTEM AND METHOD FOR CONFIGURING DRIVERS - Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.10-08-2009
20110019713SYSTEM AND METHOD FOR AUTOMATICALLY CALIBRATING A TEMPERATURE SENSOR - There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.01-27-2011
20110167193SHARING PHYSICAL MEMORY LOCATIONS IN MEMORY DEVICES - A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.07-07-2011

Patent applications by Sujeet Ayyapureddi, Boise, ID US

Sujeet Ayyapureddi US

Patent application numberDescriptionPublished
20090295426DYNAMICALLY ADJUSTING OPERATION OF A CIRCUIT WITHIN A SEMICONDUCTOR DEVICE - Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices.12-03-2009

Sujeet V. Ayyapureddi, Boise, ID US

Patent application numberDescriptionPublished
20110242925REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES - The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.10-06-2011