| Patent application number | Description | Published |
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| 20090155981 | METHOD AND APPARATUS FOR SINGULATING INTEGRATED CIRCUIT CHIPS - A method of singulating integrated circuit chips. The method includes forming, from a bottom surface of a substrate, trenches part way through the substrate in the kerf regions surrounding integrated circuit regions previously formed in the substrate; placing a top surface of the substrate on a singulation fixture having compartments, the walls of the compartments fitting into the trenches in the substrate; and thinning the bottom surface of the substrate until the individual integrated circuit regions are singulated into individual integrated circuit chips. | 06-18-2009 |
| 20090201626 | GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY - A semiconductor structure and a method for forming the same. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball. | 08-13-2009 |
| 20090218688 | OPTIMIZED PASSIVATION SLOPE FOR SOLDER CONNECTIONS - A semiconductor structure includes at least one bond pad. An insulator layer is on the surface of the semiconductor chip and on a portion of the bond pad. The polyimide layer comprises a bottom surface contacting and coplanar with the surface of the semiconductor chip, a top surface opposite and parallel to the bottom surface of the polyimide layer, and a sloped side between corresponding ends of the top surface of the polyimide layer and the bottom surface of the polyimide layer. The sloped side joins the bottom surface of the polyimide layer at the top surface of the bond pad. The sloped side of the polyimide layer forms an angle less than 50° with the bottom surface of the polyimide layer. | 09-03-2009 |
| 20090260778 | LOW PROFILE HEAT SINK FOR SEMICONDUCTOR DEVICES - A heat sink for cooling a heat-generating device includes a base and a cooling section coupled thereto for cooling the device. The cooling section includes a plurality of flow tubes, each flow tube having an inlet, an outlet, and a bounding wall that defines a closed fluid flow path from the inlet to the outlet. Each of the flow tubes includes a central axis that is substantially parallel to a reference plane of the heat-generating device. The flow tubes may be arranged in a layered stack and include a bounding wall that has a thickness that decreases with increasing distance in the layered stack. The flow tubes may also include a cross-sectional area that decreases with increasing distance in the layered stack. Furthermore, the bounding wall of the flow tubes may have a non-planar configuration in a direction generally parallel to the central axis. | 10-22-2009 |
| 20090273095 | Rectangular-Shaped Controlled Collapse Chip Connection - A rectangular-shaped controlled collapse chip connection (C | 11-05-2009 |
| 20090321914 | PRODUCTION OF INTEGRATED CIRCUIT CHIP PACKAGES PROHIBITING FORMATION OF MICRO SOLDER BALLS - Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability. | 12-31-2009 |
| 20100203655 | GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY - A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball. | 08-12-2010 |
| Patent application number | Description | Published |
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| 20090256268 | PARTIALLY UNDERFILLED SOLDER GRID ARRAYS - An electronic device and a method of forming the device. The device including a module having opposite top surface and bottom surfaces; a first set of pads on the top surface of the module and a second set of pads on the bottom surface of the module substrate, wires within the module electrically connecting the first set of pads to the second set of pads; a set of solder interconnects in electrical and physical contact with a the second set of module pads; and a dielectric underfill layer formed on the bottom surface of the module, the underfill layer filling the space between lower regions of the solder interconnects of the set of solder interconnects, upper regions of the solder interconnects of the set of solder interconnects extending past a top surface of the underfill layer. | 10-15-2009 |
| 20090273084 | OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME - A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy. | 11-05-2009 |
| 20090279275 | METHOD OF ATTACHING AN INTEGRATED CIRCUIT CHIP TO A MODULE - A method of attaching an integrated circuit chip to a module and a resultant structure. The method includes placing a solder bump tape between the chip and the module, the solder bump tape including an array of solder columns embedded in a dielectric sheet; aligning and contacting top surfaces of solder columns with respective chip pads of an array of chip pads of the chip and aligning and contacting bottom surfaces of the solder columns with respective module pads of an array of module pads; and reflowing the solder columns to form solder interconnections between chip pads and respective module pads. | 11-12-2009 |
| 20110284280 | OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME - A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy. | 11-24-2011 |
