| Patent application number | Description | Published |
|---|
| 20080211588 | Phase Error Cancellation - A noise cancellation signal is generated for a fractional-N phase-locked loop ( | 09-04-2008 |
| 20090017773 | CAPACITIVE ISOLATOR - An integrated circuit provides high voltage isolation capabilities. The circuit includes a first area containing a first group of functional circuitry located in a substrate of the integrated circuit. This circuit also includes a second area containing a second group of functional circuitry also contained within the substrate of the integrated circuit. Capacitive isolation circuitry located in the conductive layers in the integrated circuit provide a high voltage isolation link between the first group of functional circuitry and the second group of functional circuitry. The capacitive isolation circuitry distributes a first portion of the high voltage isolation signal across the first group of capacitors in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation circuitry across the second group of capacitors in the capacitive isolation circuitry. | 01-15-2009 |
| 20090039968 | DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS - A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal. | 02-12-2009 |
| 20090213914 | CAPACITIVE ISOLATION CIRCUITRY - An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link. A differential transmitter on each of the plurality of communications channels transmits the data on the first link at a selected one of a first phase and a second phase and for transmitting the data on the second link at the selected one of the first phase and the second phase. The second phase is 180 degrees out of phase with the first phase. Each of the differential transmitters controls the selection of the first phase and the second phase on each of the first link and the second link such that only the first phase or the second phase is cross coupled onto a selected communications channel from adjacent communications channels. | 08-27-2009 |
| 20090243028 | CAPACITIVE ISOLATION CIRCUITRY WITH IMPROVED COMMON MODE DETECTOR - An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver detects the received data. The detector circuit monitors the differential signal and generates a first logical output when a voltage generated responsive to the differential signal exceeds a programmable voltage threshold level and generates a second logical output when the voltage generated responsive to the differential signal falls below the programmable voltage threshold level. | 10-01-2009 |
| 20100052826 | ISOLATOR WITH COMPLEMENTARY CONFIGURABLE MEMORY - An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary. | 03-04-2010 |
| 20100117703 | MULTI-MODE SINGLE-ENDED CMOS INPUT BUFFER - Techniques reduce the effects of power supply noise on a signal provided by a single-ended complementary metal-oxide semiconductor (i.e., CMOS) input buffer circuit capable of receiving an input signal having one of a variety of acceptable formats, while generating the signal to have substantially the same duty cycle as the input signal. The techniques include one or more of AC coupling, hysteresis, and voltage biasing applied to the input buffer circuit. | 05-13-2010 |
| 20100327930 | SCHMITT TRIGGER WITH GATED TRANSITION LEVEL CONTROL - A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level. | 12-30-2010 |
| 20110050198 | LOW-POWER VOLTAGE REGULATOR - A technique for reducing power dissipation and circuit area for a high voltage application includes creating a low-voltage, local power supply for use with local circuitry. In at least one embodiment of the invention, an apparatus includes an output node configured to provide a regulated output voltage. The apparatus includes a variable current source coupled to a first power supply node, wherein the variable current source is configured to provide an output current to the output node based on a control signal on a control node. The apparatus includes a feedback circuit configured to generate the control signal based on a mirrored current. The mirrored current is a mirrored version of a residual current flowing between the output node and a second power supply node. The regulated output voltage has a voltage level less than the voltage level on the first power supply node. | 03-03-2011 |
