Patent application number | Description | Published |
20090254694 | MEMORY DEVICE WITH INTEGRATED PARALLEL PROCESSING - A method for data processing includes accepting input data words including bits for storage in a memory, which includes multiple memory cells arranged in rows and columns. The accepted data words are stored so that the bits of each data word are stored in more than a single row of the memory. A data processing operation is performed on the stored data words by applying a sequence of one or more bit-wise operations to at least one row of the memory, so as to produce a result that is stored in one or more of the rows of the memory. | 10-08-2009 |
20090254697 | MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS - An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data. | 10-08-2009 |
20090303767 | SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS - An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data. | 12-10-2009 |
20100164972 | SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS - A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory. | 07-01-2010 |
20100172190 | Processor Arrays Made of Standard Memory Cells - Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs). | 07-08-2010 |
20110013442 | USING STORAGE CELLS TO PERFORM COMPUTATION - An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry. | 01-20-2011 |
20120137060 | Multi-stage TCAM search - A method to divide a database of TCAM rules includes selecting a rule of the database having multiple don't care values and selecting a bit of the rule having a don't care value, generating two distributor rules based on the selected rule, where the selected bit has a 1 value in one of the distributor rules and a 0 in the other of the distributor rules, associating rules of the database which match each of the distributor rules with the distributor rule they match thereby to create associated databases, and repeating the steps of selecting, generating and associating on the database and the associated databases until the average number of rules in each associated database is at or below a predefined amount. A search unit includes a distributor TCAM and a DRAM search unit having a DRAM storage unit and an associated DRAM search logic unit. The DRAM storage unit has a section for each associated database, where each section is pointed to by a different distributor rule. The DRAM search unit matches the input key to one of the rules in the section pointed to by the matched distributor rule. | 05-31-2012 |
20120140540 | CHARGE SHARING IN A TCAM ARRAY - A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor. | 06-07-2012 |
20120243283 | USING STORAGE CELLS TO PERFORM COMPUTATION - A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells. | 09-27-2012 |
20120243284 | USING STORAGE CELLS TO PERFORM COMPUTATION - A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern. | 09-27-2012 |
20120246380 | NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING - A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element. | 09-27-2012 |
20120311404 | LOW DENSITY PARITY CHECK DECODER - An error correction code decoder comprising a computational memory array having at least a variable node section and a check node section, said computational memory array comprising a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on said bit and each cell implementing one node; and a controller to instruct said computational memory to perform said operations and to write the results of computations on a block of variable nodes into its associated set of blocks of check nodes and to write the results of computations on a block of check nodes into its associated set of blocks of variable nodes. | 12-06-2012 |