| Patent application number | Description | Published |
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| 20090110567 | Air Compressor - A compact lightweight air compressor is provided with a DC motor to provide versatile use in the field where no AC power source is available. The air compressor includes a intercooler storage vessel for cooling and storing the compressed air as well as a cooling fan arrangement that allows cooling of all the air compressor components. | 04-30-2009 |
| 20090134372 | Integrated Air Compressor and Winch - An integrated air compressor and winch is provided that utilizes a source of rotary motive power for driving both a winch drum and compressor mechanism. The integrated air compressor and winch is preferably provided with a gear case that is operable to provide an appropriate gear reduction for driving the winch drum while providing an appropriate drive speed for operating the compressor. | 05-28-2009 |
| 20090309082 | Fan Cooled Winch - A winch may include a drum, a winch motor adapted to rotatably drive the drum in a first direction and a second direction, a cable adapted to be wound off of and onto the drum, and a fan including an impeller selectively driven by a fan motor. The fan is adapted to cool the winch motor. | 12-17-2009 |
| 20100059352 | Weld Breaking Contactor - An electric contactor may include a first plunger member supporting a first contact member thereon, the first plunger member being movable between a disengaged position and an engaged position with respect to a first electrical terminal; a second plunger member supporting a second contact member thereon, the second plunger member being movable between a disengaged position and an engaged position with respect to a second electrical terminal; a first linear actuator selectively causing movement of the first plunger from the disengaged position to the engaged position; and a second linear actuator selectively causing movement of the second plunger from the disengaged position to the engaged position. Actuation of one of the first and second linear actuators will apply a weld breaking force against the plunger associated with the other of the first and second linear actuators. | 03-11-2010 |
| Patent application number | Description | Published |
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| 20090100229 | Method for Increasing Cache Directory Associativity Classes in a System With a Register Space Memory - In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory. The original system address is normalized by removing address space corresponding to a memory hole, thereby generating a normalized address. The normalized address is stored in the cache directory. The normalized address is de-normalized, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data. The de-normalized address is sent to the memory system for coherency management. | 04-16-2009 |
| 20090193199 | Method for Increasing Cache Directory Associativity Classes Via Efficient Tag Bit Reclaimation - In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an memory space. An amount of memory that is in an actually configured portion of the memory space is determined. A minimum number of bits necessary to address each memory location in the actually configured portion of the memory space is determined. Each address tag is configured in each associativity class to include the minimum number of bits necessary to address each memory location in the actually configured portion of the memory space. The cache directory is configured to include a maximum number of associativity classes per line in the cache directory. | 07-30-2009 |
| 20090265534 | Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel Looping - A method, apparatus, and computer program are provided for assessing fairness, performance, and livelock in a logic development process utilizing comparative parallel looping. Multiple loop macros are generated, the multiple loop macros respectively correspond to multiple processor threads, and the multiple loop macros are parallel comparative loop macros. The multiple processor threads for the multiple loop macros are executed in which a common resource is accessed. A forward performance of each of the multiple processor threads is verified. The forward performance of the multiple processor threads is compared with each other. It is determined whether any of the multiple processor threads fails to meet a minimum loop count or a minimum loop time. It is determined whether any of the multiple processor threads exceeds a maximum loop count or a maximum loop time. It is recognized whether fairness is maintained during the execution of the multiple processor threads. | 10-22-2009 |
| 20090271165 | Simultaneous Parameter-Driven and Deterministic Simulation With or Without Synchronization - A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design. | 10-29-2009 |
| Patent application number | Description | Published |
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| 20100332767 | Controllably Exiting An Unknown State Of A Cache Coherency Directory - In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed. | 12-30-2010 |
| 20110078384 | MEMORY MIRRORING AND MIGRATION AT HOME AGENT - Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed. | 03-31-2011 |
| 20110078492 | HOME AGENT DATA AND MEMORY MANAGEMENT - Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed. | 03-31-2011 |
