| Patent application number | Description | Published |
|---|
| 20080265247 | UNIFIED TEST STRUCTURE FOR STRESS MIGRATION TESTS - A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration. | 10-30-2008 |
| 20080297188 | IC CHIP STRESS TESTING - Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current I | 12-04-2008 |
| 20100107403 | SEMICONDUCTOR DEVICE COMPRISING eFUSES OF ENHANCED PROGRAMMING EFFICIENCY - In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished. | 05-06-2010 |
| 20100133700 | PERFORMANCE ENHANCEMENT IN METALLIZATION SYSTEMS OF MICROSTRUCTURE DEVICES BY INCORPORATING GRAIN SIZE INCREASING METAL FEATURES - In a sophisticated metallization system, enhanced electromigration behavior may be accomplished by incorporating electromigration barriers into metal lines after a given distance, which may be accomplished by providing an increased width in order to obtain an enhanced average grain size in the intermediate metal regions of increased lateral width. Consequently, the electromigration induced material diffusion may encounter an overall increased grain size along the entire depth of the metal lines, thereby resulting in a significantly reduced electromigration effect and thus enhanced reliability of the critical metal lines. | 06-03-2010 |
| 20100134125 | BUILT-IN COMPLIANCE IN TEST STRUCTURES FOR LEAKAGE AND DIELECTRIC BREAKDOWN OF DIELECTRIC MATERIALS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - In a test structure for determining dielectric breakdown events of a metallization system of semiconductor devices, a built-in compliance functionality may allow reliable switching off of the test voltage prior to causing high leakage currents, which may conventionally result in significant damage. Consequently, further failure analysis may be possible after the occurrence of a dielectric breakdown event. | 06-03-2010 |
| 20100221911 | PROVIDING SUPERIOR ELECTROMIGRATION PERFORMANCE AND REDUCING DETERIORATION OF SENSITIVE LOW-K DIELECTRICS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials. | 09-02-2010 |
| 20110049727 | RECESSED INTERLAYER DIELECTRIC IN A METALLIZATION STRUCTURE OF A SEMICONDUCTOR DEVICE - In a complex metallization system, the probability of dielectric breakdown may be reduced by vertically separating a critical area of high electric field strength and an area of reduced dielectric strength of the interlayer dielectric material. For this purpose, the interlayer dielectric material may be recessed after forming the metal regions and/or the metal regions may be increased in height and the corresponding recess may be refilled with an appropriate dielectric material. | 03-03-2011 |
| 20110156858 | SEMICONDUCTOR DEVICE COMPRISING METAL-BASED eFUSES OF ENHANCED PROGRAMMING EFFICIENCY BY ENHANCING METAL AGGLOMERATION AND/OR VOIDING - Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures. | 06-30-2011 |
