| Patent application number | Description | Published |
|---|
| 20090067222 | SEMICONDUCTOR MEMORY DEVICE - SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor. | 03-12-2009 |
| 20090147561 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell array having a plurality of SRAM cells arranged along a pair of bit lines that extend along a first direction. A read circuit is arranged for each column at one side of the memory cell array and detects a potential of any one of the pair of bit lines. A write circuit is arranged, separately from the read circuit, at the other side of the memory cell array. The write circuit provides written data to the pair of bit lines to write data to the SRAM cells. | 06-11-2009 |
| 20090168500 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines, | 07-02-2009 |
| 20100046279 | SEMICONDUCTOR MEMORY DEVICE AND TRIMMING METHOD THEREOF - The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors. | 02-25-2010 |
| 20100054025 | SEMICONDUCTOR INTEGRATED MEMORY CIRCUIT AND TRIMMING METHOD THEREOF - A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node. | 03-04-2010 |
| 20100165697 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting with the first wirings, and a plurality of memory cells respectively arranged at intersections of the first and second wirings; a plurality of drivers that drive the first wirings; a dummy wiring continuously extending in a direction of the first wirings and in a direction of the second wirings, a part of the dummy wiring extending in the direction of the second wirings being connected to the plurality of drivers; a plurality of switch circuits connected to respective connection portions of the plurality of drivers and the dummy wiring; and a replica line extending in the direction of the second wirings and connected to the dummy wiring through the plurality of switch circuits. | 07-01-2010 |
| 20100165771 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, a memory cell array having a plurality of memory cell each provided at an intersection of the word line and the bit line, a plurality of sense amplifier each of which detects and amplifies a signal level of the bit line, a replica word line, a replica bit line intersecting the replica word line, a replica memory cell provided at each intersection of the replica word line and the replica bit line, a replica circuit which simulates reading out of the memory cell, and a timing generating circuit which quantizes a replica delay time that is a time until the replica bit line changes from a reference timing, and which generates an activation timing for the sense amplifier based on a quantization result. | 07-01-2010 |
| 20110013468 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SAME - A memory cell is provided at an intersection of a word line and a bit line. A sense amplifier circuit senses and amplifies a signal on the bit line. Replica circuits include a replica cell configured to retain certain data fixedly. A signal detection circuit detects an output signal that rises up at the latest timing among output signals output from the plurality of replica circuits respectively and outputs a detection signal. A delay circuit delays the detection signal. The sense amplifier circuit is activated based on the delayed signal. | 01-20-2011 |
