Patent application number | Description | Published |
20080227241 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a <110> direction. These wafers are surface-bonded together so that the <110>directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in <110> direction to the upper wafer, and the other of which is equal in <110> direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained. | 09-18-2008 |
20080315183 | SEMICONDUCTOR DEVICE WITH CARBON NANOTUBE CHANNEL AND MANUFACTURING METHOD THEREOF - A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched therebetween, and a pair of source and drain regions interposing the channel region therebetween. The source and drain regions have portions in contact with the channel region, which portions are made of a specific semiconductor material that is wider in energy band gap than the channel region. | 12-25-2008 |
20090008726 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer. | 01-08-2009 |
20090325357 | Semiconductor device and method of manufacturing the same - A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films. | 12-31-2009 |
20110049611 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In a memory cell portion, a stacked structure, in which dielectric layers and semiconductor layers are alternately stacked, is arranged in a fin shape on a semiconductor substrate, and in a peripheral circuit portion, a gate electrode is arranged on the semiconductor substrate via a gate dielectric film so that a height of an upper surface of the gate electrode is set to be substantially equal to a height of an upper surface of the stacked structure in which the dielectric layers and the semiconductor layers are alternately stacked. | 03-03-2011 |
20120077341 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed. | 03-29-2012 |
20130076550 | ANALOG-TO-DIGITAL CONVERTER - According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal. | 03-28-2013 |
20130076551 | ANALOG-TO-DIGITAL CONVERTER - According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal. | 03-28-2013 |
20130250686 | SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND CONTROL METHOD - According to an embodiment, a semiconductor memory device includes a first storage unit, a receiving unit, an acquiring unit, and an output control unit. The first storage unit is configured to store a value and address information in which a key address generated on the basis of a key associated with the value and a physical address of the value are associated with each other. The receiving unit is configured to receive a request for acquisition of the value associated with the key. The request contains the key. The acquiring unit is configured to acquire the physical address associated with the key address of the key contained in the request for acquisition on the basis of the address information. The output control unit is configured to acquire the value at the acquired physical address from the first storage unit and output the acquired value in response to the request. | 09-26-2013 |
20130254240 | METHOD OF PROCESSING DATABASE, DATABASE PROCESSING APPARATUS, COMPUTER PROGRAM PRODUCT - According to an embodiment, a method of processing a database includes dividing a first data table that includes records including data in a plurality of columns into a plurality of second data tables based on a predetermined criterion for dividing columns. Each of the second data tables includes data in at least one column. The method also includes dividing each of the second data tables into a plurality of third data tables based on a predetermined criterion for dividing data in units of a record based on the data. Each of the third data tables includes at least one record. The method also includes storing the third data tables in a plurality of storage units, respectively. Each of the storage units allows the data to be read independently. | 09-26-2013 |
20130346825 | ERROR CORRECTION DEVICE, ERROR CORRECTION METHOD AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1, Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first, messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1. | 12-26-2013 |
20140025865 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device includes a controller and a second storage unit. The controller is configured to control a write process of writing data into a first storage unit in which data supplied from a host device are stored or a read process of reading the data stored in the first storage in response to a request from the host device. The second storage unit is temporarily used in the write process or the read process. The second storage unit includes a nonvolatile third storage unit having an area for storing a duplicate of the data to be written by the write process; and a nonvolatile fourth storage unit having a work area for the write process or the read process and having a higher read/write speed than the third storage unit. | 01-23-2014 |
20140035618 | CIRCUIT HAVING PROGRAMMABLE MATCH DETERMINATION FUNCTION, AND LUT CIRCUIT, MUX CIRCUIT AND FPGA DEVICE WITH SUCH FUNCTION AND METHOD OF DATA WRITING - A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line. | 02-06-2014 |
20140055189 | MIXER CIRCUIT, SEMICONDUCTOR DEVICE, RECEIVING CIRCUIT, RECEIVING DEVICE, AND COMMUNICATION DEVICE - According to an embodiment, a mixer circuit includes first transistors each having a charge storage layer, a second transistor, a group of first nodes, and an output node. The first transistors as a pair receive a differential signal having a first frequency. The second transistor receives a signal having a second frequency. The group of first nodes makes the charge storage layer of at least any one of the first transistors store charge during non-operation period during which the differential signal having the first frequency and the signal having the second frequency are not mixed and reduces loss of the charge during operation period during which those signals are mixed, to adjust a threshold voltage of at least any one of the first transistors from outside. The output node outputs a signal resulting from mixing the differential signal having the first frequency and the signal having the second frequency. | 02-27-2014 |
20140195710 | STORAGE DEVICE - According to one embodiment, a storage device includes a processing unit and a plurality of storage units. The processing unit includes a processor and a network communication unit. The storage unit includes a processor input/output port connected to the processing unit via a bus, a storage-unit input/output port connected to adjacent storage unit thereto, a memory capable of storing data, and a routing unit configured to perform a transfer process by determining a transfer route of the data to another one of the storage units on the basis of positional information of the storage unit included in the data. | 07-10-2014 |
20140201439 | STORAGE DEVICE AND STORAGE METHOD - According to an embodiment, a storage device includes a plurality of memory nodes and a control unit. Each of the memory nodes includes a storage unit including a plurality of storage areas having a predetermined size. The memory nodes are connected to each other in two or more different directions. The memory nodes constitute two or more groups each including two or more memory nodes. The control unit is configured to sequentially allocate data writing destinations in the storage units to the storage areas respectively included in the different groups. | 07-17-2014 |