# Atsufumi Shibayama, Tokyo JP

## Atsufumi Shibayama, Tokyo JP

Patent application number | Description | Published |
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20080218225 | Semiconductor Device and Communication Control Method - The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores. | 09-11-2008 |

20100042373 | SIGNAL MEASURING DEVICE AND SIGNAL MEASURING METHOD - A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal. | 02-18-2010 |

20100052740 | CLOCK SIGNAL FREQUENCY DIVIDING CIRCUIT AND CLOCK SIGNAL FREQUENCY DIVIDING METHOD - To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and Mare integers, includes an output clock selecting circuit ( | 03-04-2010 |

20100052753 | CLOCK SIGNAL DIVIDING CIRCUIT - A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit. | 03-04-2010 |

20110089981 | SEMICONDUCTOR DEVICE AND COMMUNICATION METHOD - It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit. The communication timing control circuit generates the communication timing signal determined by a frequency ratio information and a phase relation information, the frequency ratio information setting a frequency ratio of the first clock signal to the second clock signal, the phase relation information indicating a phase relation between the first clock signal and the second clock signal. | 04-21-2011 |

20110187418 | CLOCK SIGNAL FREQUENCY DIVIDING CIRCUIT AND METHOD - A mask circuit ( | 08-04-2011 |

20110193596 | CLOCK FREQUENCY DIVIDER CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK FREQUENCY DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD - A clock frequency divider circuit | 08-11-2011 |

20110200162 | CLOCK FREQUENCY DIVIDER CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK FREQUENCY DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD - To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal. | 08-18-2011 |

20120096300 | COMMUNICATION CIRCUIT AND COMMUNICATION METHOD - Provided is a communication circuit ( | 04-19-2012 |

20120098583 | PIPELINE CIRCUIT, SEMICONDUCTOR DEVICE, AND PIPELINE CONTROL METHOD - Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock frequency is decreased, and in response to performance requests for a processing throughput. Among P clocks (P is a positive integer), the phases of which are delayed in the order from a first clock to a P-th clock, for example, among six clocks of P | 04-26-2012 |

20120117337 | SEMICONDUCTOR INTEGRATED CIRCUIT AND EXPONENT CALCULATION METHOD - Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data. | 05-10-2012 |

20130194008 | CLOCK FREQUENCY DIVIDER CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK FREQUENCY DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD - To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal. | 08-01-2013 |

20130262545 | DIGITAL FILTER CIRCUIT AND DIGITAL FILTER CONTROL METHOD - [Objective] | 10-03-2013 |

20140089361 | ARITHMETIC PROCESSING APPARATUS AND AN ARITHMETIC PROCESSING METHOD - Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision. | 03-27-2014 |

20140379771 | DIGITAL FILTER CIRCUIT AND DIGITAL FILTER PROCESSING METHOD - A digital filter circuit includes an FFT circuit ( | 12-25-2014 |

20150019608 | DIGITAL FILTER CIRCUIT, DIGITAL FILTER PROCESSING METHOD AND DIGITAL FILTER PROCESSING PROGRAM STORAGE MEDIUM - Reduction of a circuit size and power consumption for performing digital filtering processing in a frequency domain is realized. The digital filter circuit includes: a complex conjugate generation unit for generating a second complex number signal including conjugate complex numbers of all complex numbers included in a first complex number signal of the frequency domain generated by converting a complex number signal of a time domain by Fourier transform; a filter coefficient generation unit for generating a first and a second frequency domain filter coefficient of a complex number from a first, a second and a third input filter coefficient of a complex number having been inputted; a first filtering unit for performing filtering processing to the first complex number signal by the first frequency domain filter coefficient, and outputting a third complex number signal; a second filtering unit for performing filtering processing to the second complex number signal by the second frequency domain filter coefficient, and outputting a fourth complex number signal; and a complex conjugate combining unit for combining the third complex number signal and the fourth complex number signal, and generating a fifth complex number signal. | 01-15-2015 |