Assche
Gert Van Assche, Neerlinter BE
Patent application number | Description | Published |
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20120265711 | Systems and Methods for Determining a Risk-Reduced Word Price for Editing - Systems and methods for determining a risk-reduced word price for editing. The editing can be of a document, for example, that has been translated by a human or a machine. A system and method may include providing to one or more preferred editors a first portion of editing jobs from a batch job. In some aspects, the system and method may include receiving an editing time of the one or more preferred editors editing the first portion of editing jobs. In further aspects, the system and method can include calculating a word price for editing a remaining portion of editing jobs of the batch job based on the editing time. | 10-18-2012 |
20130103381 | SYSTEMS AND METHODS FOR ENHANCING MACHINE TRANSLATION POST EDIT REVIEW PROCESSES - Systems and methods for enhancing machine translation post edit review processes are provided herein. According to some embodiments, methods for displaying confidence estimations for machine translated segments of a source document may include executing instructions stored in memory, the instructions being executed by a processor to calculate a confidence estimation for a machine translated segment of a source document, compare the confidence estimation for the machine translated segment to one or more benchmark values, associate the machine translated segment with a color based upon the confidence estimation for the machine translated segment relative to the one or more benchmark values, and provide the machine translated segment having the color in a graphical format, to a client device. | 04-25-2013 |
Gilles Van Assche, Bruxelles BE
Patent application number | Description | Published |
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20080219400 | Event Counter - A counting method and a counter using an integrated circuit memory area, including at least one step of storage of partial values in several words of identical memory sizes, the result of the counting being obtained by arithmetically adding the values contained in the different words. | 09-11-2008 |
20100306295 | PROTECTION OF A PRIME NUMBER GENERATION FOR AN RSA ALGORITHM - A method for protecting a generation, by an electronic circuit, of at least one prime number by testing the prime character of successive candidate numbers, including: for each candidate number: the calculation of a reference number involving at least one first random number, and at least one primality test based on modular exponentiation calculations; and for a candidate number having successfully passed the primality test: a test of consistency between the candidate number and its reference number. | 12-02-2010 |
Gilles Van Assche, Woluwe-St-Lambert BE
Patent application number | Description | Published |
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20120284533 | METHOD AND CIRCUIT FOR CRYPTOGRAPHIC OPERATION - A method of performing a cryptographic operation including: receiving a plurality of binary input values; splitting the binary input values into a plurality of non-binary digits of base r, where r is an integer greater than 2 and not equal to a power of 2; and performing, by a cryptographic block on each of the plurality of non-binary digits, a different modulo r operation to generate at least one output digit) of base r. | 11-08-2012 |
20130159791 | METHOD AND DEVICE FOR FAULT DETECTION - The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device. | 06-20-2013 |
Tom Van Assche, Brussegem BE
Patent application number | Description | Published |
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20120271379 | INTER-CHIP COMMUNICATIONS FOR IMPLANTABLE STIMULATING DEVICES - A device including a first integrated circuit (IC), a second IC configured to provide instructions to the first IC based on received data, wherein the first IC is a high-voltage IC and the second IC is a low-voltage IC, and a communication interface between the first and second ICs including a data bus of parallel data lines. The second IC is configured to select, based on the received data, one of a plurality of different communication modes for providing the instructions to the first IC via the communication interface, wherein each mode is defined by a quantity of address data and a quantity of configuration data used to provide the instructions to the first IC. | 10-25-2012 |
20140047154 | INTER-CHIP COMMUNICATIONS FOR IMPLANTABLE STIMULATING DEVICES - A device including a first integrated circuit (IC), a second IC configured to provide instructions to the first IC based on received data, wherein the first IC is a high-voltage IC and the second IC is a low-voltage IC, and a communication interface between the first and second ICs including a data bus of parallel data lines. The second IC is configured to select, based on the received data, one of a plurality of different communication modes for providing the instructions to the first IC via the communication interface, wherein each mode is defined by a quantity of address data and a quantity of configuration data used to provide the instructions to the first IC. | 02-13-2014 |