Patent application number | Description | Published |
20080239807 | Transition areas for dense memory arrays - A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F. | 10-02-2008 |
20080266954 | Transition areas for dense memory arrays - A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F. | 10-30-2008 |
20090065841 | SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLS - An improved contact etch stop liner (CESL) is provided, to reduce stress effects in NVM cells using a nitride charge-trapping layer (such as NROM). SiON (silicon oxy-nitride) may be used in lieu of SiN (silicon nitride), for the CESL. Or, the CESL may be processed to be discontinuous, to reduce stress effects, using either conventional SiN (silicon nitride) or SiON. Or, the CESL layer may be eliminated entirely, to reduce stress effects. | 03-12-2009 |
20090109755 | Neighbor block refresh for non-volatile memory - Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a sub-population of Vt distributions at a given program level. Various timings and strategies for performing the refresh operation are disclosed. The effects of word line disturb (gate disturb) may thereby be reduced. | 04-30-2009 |
20090175089 | Retention in NVM with top or bottom injection - Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS. | 07-09-2009 |
20090201741 | Non-volatile memory cell with injector - In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the source of holes into the charge-storage layer of the charge storage stack. The injector has a barrier potential for holes which is less than an insulating layer of the charge-storage stack which is oriented towards the source of holes. A multi-layer crested barrier injector may have layers of increasing potential barriers for holes from the source to the charge-storage layer. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS. | 08-13-2009 |
20100173464 | Non-volatile memory structure and method of fabrication - A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns. | 07-08-2010 |
20120127796 | RETENTION IN NVM WITH TOP OR BOTTOM INJECTION - Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS. | 05-24-2012 |