| Patent application number | Description | Published |
|---|
| 20090052266 | TEMPERATURE THROTTLING MECHANISM FOR DDR3 MEMORY - A method for throttling a bus, e.g. a memory bus, may be used to compensate for potential inaccuracy of feedback information received for monitored characteristics, e.g. temperature, reported by sensors configured in monitored devices, e.g. memory devices, accessed through the bus. For example, in case of a memory bus, a memory controller may be configured to throttle the memory bus in a way that maximizes system performance while ensuring that the memory devices keep operating within their thermal limits. Readings obtained from the memory, or from close proximity to the memory, may indicate whether the temperature of the memory has crossed over one or more designated trip points, and one or more algorithms may be executed to perform throttling according to the readings and based on fixed and dynamic throttling modes. The memory controller may infer temperature changes taking place in the memory devices when successive readings are indicating that the temperature of the memory device has remained over a given trip point. Based on these inferences, the memory controller may then change the manner in which the bus is throttled. | 02-26-2009 |
| 20090055570 | DETECTION OF SPECULATIVE PRECHARGE - A DRAM controller may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM, and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open. If the page is not closed as a result of the determination and/or prediction, it may be left open and closed after it has remained idle a specified length of time following the last access to the page. | 02-26-2009 |
| 20090055572 | OPTIMAL SOLUTION TO CONTROL DATA CHANNELS - A DRAM controller may comprise two sub-controllers, each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128-bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a “copy” of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the BIOS has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel. | 02-26-2009 |
| 20090244997 | Method for Training Dynamic Random Access Memory (DRAM) Controller Timing Delays - Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller ( | 10-01-2009 |
