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Ashtiani
Kaihan Ashtiani, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100159694 | METHOD FOR DEPOSITING THIN TUNGSTEN FILM WITH LOW RESISTIVITY AND ROBUST MICRO-ADHESION CHARACTERISTICS - Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage. | 06-24-2010 |
| 20110151678 | NOVEL GAP FILL INTEGRATION - Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps. | 06-23-2011 |
Kaihan Ashtiani, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080254623 | METHODS FOR GROWING LOW-RESISTIVITY TUNGSTEN FOR HIGH ASPECT RATIO AND SMALL FEATURES - The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 μΩ-cm for a 500 Angstrom film may be obtained. | 10-16-2008 |
| 20090163025 | METHODS FOR FORMING ALL TUNGSTEN CONTACTS AND LINES - Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation. | 06-25-2009 |
Pouya Ashtiani, Richmond Hill CA
| Patent application number | Description | Published |
|---|---|---|
| 20110068632 | INTEGRATED CIRCUIT ADAPTED TO BE SELECTIVELY AC OR DC COUPLED - An integrated circuit is adapted to be selectively AC or DC coupled to an external device at a coupling point. The integrated circuit includes a first connector connected to the coupling point by way of a coupling capacitor for AC coupling, a second connector connected to the coupling point for DC coupling, and a switch to selectively short the first and second connectors and thereby the coupling capacitor, when the integrated circuit is DC coupled to the device. The switch may be a MOSFET bridge comprising a switch control MOSFET interconnected between the first and second connectors, with the switch control MOSFET receiving at its gate a mode status signal for turning on the switch control MOSFET and thereby shorting the MOSFET bridge when the integrated circuit is DC coupled to the external device. The MOSFET bridge also includes a number of dynamically biased nMOSFETs connected in series with the switch control MOSFET in order to protect switch control MOSFET from high external supply voltages, and a number of dynamically biased pMOSFETs connected in parallel with the switch control MOSFET. | 03-24-2011 |