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Ashrafzadeh
Ahmad Ashrafzadeh, Morgan Hill, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100013011 | VERTICAL MOSFET WITH THROUGH-BODY VIA FOR GATE - In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface. The first surface of the first vertical MOSFET and the second surface of the second vertical MOSFET are substantially co-planar and an electrically conductive can substantially surrounds the MOSFETS and shorts the first surface of the first vertical MOSFET to the second surface of the second vertical MOSFET. | 01-21-2010 |
| 20100102416 | Integrated Circuit Packages Incorporating an Inductor and Methods - Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed. | 04-29-2010 |
| 20110227153 | Vertical Mosfet with Through-Body Via for Gate - In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface. The first surface of the first vertical MOSFET and the second surface of the second vertical MOSFET are substantially co-planar and an electrically conductive can substantially surrounds the MOSFETS and shorts the first surface of the first vertical MOSFET to the second surface of the second vertical MOSFET. | 09-22-2011 |
Ahmad Ashrafzadeh, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080231342 | PROGRAMMABLE CALIBRATION CIRCUIT FOR POWER SUPPLY CURRENT SENSING AND DROOP LOSS COMPENSATION - A circuit for regulating power is disclosed. The present invention provides circuits and methods for current sensing variations, static droop settings, mismatched phase outputs, and temperature variations in a multiphase power regulator. The circuits may include a calibration controller that senses and regulates both a current sensing circuit and the droop in a power regulator over a range of temperatures thus equalizing phase outputs. The present invention includes the schematic organization and implementation of the circuit, the circuit's calibration, its use, and implementation. This invention advantageously provides circuits and methods to properly power a processor or IC chip according to the unique power specifications of the processor or chip. | 09-25-2008 |
Ahmad R. Ashrafzadeh, Morgan Hill, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100072615 | High-Electrical-Current Wafer Level Packaging, High-Electrical-Current WLP Electronic Devices, and Methods of Manufacture Thereof - The present invention has various aspects relating to the maximization of current carrying capacity of wafer level packaged chip scale solder pad mounted integrated circuits. In one aspect, the solder pad areas are maximized by using rectangular solder pads spaced as close together as reliable mounting to a circuit board will allow. In another aspect, multiple contact pads may be used for increasing the current capacity without using contact pads of different areas. In still another aspect, vias are used to directly connect one lead of high current component or components to a contact pad directly above that component, and to route a second lead of the high current component to an adjacent contact pad by way of a thick metal interconnect layer. | 03-25-2010 |
Ali Ashrafzadeh, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120078659 | METHOD AND SYSTEM FOR FACILITATING CLINICAL RESEARCH - A method of facilitating clinical research. The method includes receiving at least one research criteria and at least one comparison criteria, e.g., demographical information, patient characteristic, patient health, type of drug, drug classification, insurance type, etc. A database storing medical records associated with patients may be accessed. Information within the database may be filtered based on the research criteria to identify a group of patients. The information within medical records of the group of patients is processed to generate processed information, wherein the information is associated with the at least one comparison criteria. The processed information is output, e.g., to a memory component for storage, to a display for rendering, etc. The processing may include purging confidential information associated with the group of patients according to HIPAA. A number may be assigned to each patient within the group of patients for identification thereof. | 03-29-2012 |