Patent application number | Description | Published |
20090050468 | CONTROLLED SURFACE OXIDATION OF ALUMINUM INTERCONNECT - An aluminum interconnect metallization for an integrated circuit is controllably oxidized in a pure oxygen ambient with the optional addition of argon. It is advantageously performed as the wafer is cooled from above 300° C. occurring during aluminum sputtering to less than 100° C. allowing the aluminized wafer to be loaded into a plastic cassette. Oxidation may controllably occur in a pass-through chamber between a high-vacuum and a low-vacuum transfer chamber. The oxygen partial pressure is advantageously in the range of 0.01 to 1 Torr, preferably 0.1 to 0.5 Torr. The addition of argon to a total pressure of greater than 1 Torr promotes wafer cooling when the wafer is placed on a water-cooled pedestal. To prevent oxygen backflow into the sputter chambers, the cool down chamber is not vacuum pumped during cooling and first argon and then oxygen are pulsed into the chamber. | 02-26-2009 |
20110212256 | DEPOSITION RATE CONTROL - An vapor deposition control system includes a multi-level control scheme. | 09-01-2011 |
20120017973 | IN-LINE DEPOSITION SYSTEM - A deposition system includes a load lock chamber for receiving a substrate and exposing a substrate to a load lock temperature and load lock pressure suitable to prepare a substrate for subsequent low-pressure and high-temperature processing or for ambient temperature and pressure conditions. | 01-26-2012 |
20120021556 | DEPOSITION SYSTEM - A selenium deposition system can improve the selenium vapor distribution. | 01-26-2012 |
20120058576 | Deposition System - A pumping and valve control device can be used in an atomic layer deposition system. | 03-08-2012 |
20140262749 | Methods of Plasma Surface Treatment in a PVD Chamber - Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma processing can be performed in a same process chamber. The process chamber, configured to perform sputter deposition and plasma processing, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap. The plasma processing may include plasma etching or plasma surface treatment. | 09-18-2014 |
20150061027 | METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS - One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities. | 03-05-2015 |
20150091105 | CONTINUOUS TUNING OF ERBIUM SILICIDE METAL GATE EFFECTIVE WORK FUNCTION VIA A PVD NANOLAMINATE APPROACH FOR MOSFET APPLICATIONS - Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nano-laminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack. | 04-02-2015 |
20150093887 | METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITSI - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeO | 04-02-2015 |
20150093889 | METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeO | 04-02-2015 |
20150093914 | METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeO | 04-02-2015 |