| Patent application number | Description | Published |
|---|
| 20080201494 | Controlling complex non-linear data transfers - A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data. | 08-21-2008 |
| 20090132863 | Packing trace protocols within trace streams - A data processing apparatus is provided with packing circuitry | 05-21-2009 |
| 20090187790 | Generation of trace elements within a data processing apparatus - A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation. A trace analysing apparatus can then be provided to reconstruct such omitted information based on a tracked architectural state value of the relevant item of architectural state. | 07-23-2009 |
| 20090282304 | Debug circuitry - An apparatus for processing data includes diagnostic mechanisms for providing watch point and breakpoint functionality. Semaphores are associated with the watch points and are provided with hardware support within the diagnostic circuitry serving to monitor whether or not accesses to watch point data is being made in accordance with the permissions set up and noted in the semaphore data. | 11-12-2009 |
| 20100223518 | Diagnostic mode switching - A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active. | 09-02-2010 |
| 20100299562 | Reducing bandwidth required for trace data - A data processing apparatus is disclosed including trace logic for monitoring behaviour of a portion of said data processing apparatus and prediction logic for providing at least one prediction as to at least one step of the behavior of the portion of the data processing apparatus. The trace logic monitors behavior of the portion of the data processing apparatus, determines from the monitored behaviour whether the at least one prediction is correct, and outputs a prediction indicator indicating whether the at least one prediction is correct. | 11-25-2010 |
| 20100325317 | Controlling complex non-linear data transfers - A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data. | 12-23-2010 |
| 20110219376 | Method, apparatus and trace module for generating timestamps - The present invention relates to the field of data processing, in particular, a method, apparatus | 09-08-2011 |
