Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Asaro
Anthony Asaro, Toronto CA
| Patent application number | Description | Published |
|---|---|---|
| 20080250212 | METHOD AND APPARATUS FOR ACCESSING MEMORY USING PROGRAMMABLE MEMORY ACCESSING INTERLEAVING RATIO INFORMATION - A method and apparatus stores data representing a non 1:1 memory access interleaving ratio for accessing a plurality of memories. The method and apparatus interleaves memory accesses to at least either a first memory that is accessible via a first (and associated memory) bus having first characteristics or a second memory accessible via a second bus having different characteristics, based on the data representing the non 1:1 interleaving memory access ratio. | 10-09-2008 |
| 20100162256 | OPTIMIZATION OF APPLICATION POWER CONSUMPTION AND PERFORMANCE IN AN INTEGRATED SYSTEM ON A CHIP - A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different. | 06-24-2010 |
| 20110057939 | Reading a Local Memory of a Processing Unit - Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit. | 03-10-2011 |
Anthony Asaro, Scarborough CA
| Patent application number | Description | Published |
|---|---|---|
| 20090077274 | Multi-Priority Communication in a Differential Serial Communication Link - A circuit includes a high priority circuit and a non-high priority circuit. The high priority circuit is operative to communicate high priority information to a single path of a differential serial communication link. The non-high priority circuit communicates non-high priority information to the single path. The high priority information is communicated prior to the non-high priority information. In one example, the circuit includes a flow control distributor operatively coupled to the high priority circuit and the non-high priority circuit. The flow control distributor distributes a total number of flow control credits into high priority credits and non-high priority credits. The flow control distributor controls communication of the high priority information based on the high priority credits. The flow control distributor controls communication of the non-high priority information based on the non-high priority credits. | 03-19-2009 |
| 20090307406 | Memory Device for Providing Data in a Graphics System and Method and Apparatus Thereof - A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. | 12-10-2009 |
Antonio Asaro, Toronto CA
| Patent application number | Description | Published |
|---|---|---|
| 20100281231 | HIERARCHICAL MEMORY ARBITRATION TECHNIQUE FOR DISPARATE SOURCES - A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream. | 11-04-2010 |
Donna Asaro, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090006163 | Method and System for Allocating Member Compensation - Compensation to be paid to one or more members of an organization is determined. The organization has members organized in a hierarchical structure comprising first-level members, second-level members, and third-level members. A pool of money to be paid to the members in the organization as compensation is identified. A first portion of the pool is assigned to a first-level member. Then the first-level member determines a second portion of the pool from the first portion to be distributed to members below the first-level member and/or an amount from the first portion to be paid to one or more members below the first-level member. The second portion is assigned to the second-level member. Then the second-level member determines a third portion of the pool to be distributed to members below the second-level member and/or an amount from the second portion to be paid to members below the second-level member. | 01-01-2009 |
Marianna F. Asaro, Belmont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090143632 | SORBENTS AND PROCESSES FOR SEPARATION OF OLEFINS FROM PARAFFINS - In one embodiment, the present invention relates generally to a method for separating olefins from paraffins. In one embodiment, the method includes providing a mixture comprising olefins and paraffins, providing a gas separation agent to associatively, reversibly and selectively bind the olefin and dissociating the olefin from the gas separation agent. | 06-04-2009 |
| 20100326272 | METHOD AND APPARATUS FOR GAS REMOVAL - Aspects of the invention include a method and apparatus for reversibly sorbing a target gas. In one embodiment, an apparatus for reversibly sorbing a target gas is disclosed. The apparatus includes an inlet, a multi-channel monolith coupled to the inlet, the multi-channel monolith including a plurality of channels, each one of the plurality of channels includes one or more walls, wherein at least one of the one or more walls of at least one of the plurality of channels is porous and wherein one or more of the plurality of channels contain a sorbent and an outlet coupled to the multi-channel monolith. | 12-30-2010 |
Michael Asaro, Flagstaff, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110117338 | OPEN PORE CERAMIC MATRIX COATED WITH METAL OR METAL ALLOYS AND METHODS OF MAKING SAME - Open pore foams are coated with metal or metal alloys by electrolytic or electroless plating. The characteristics of the plating bath are adjusted to decrease the surface tension such that the plate bath composition can pass into the pores of the foam, preferably at least two and most preferably more than five pores in depth from the surface of the foam matrix. This can be accomplished by adding a surfactant, solvent or other constituent to reduce the surface tension of the plate bath. In addition, heat and pressure can be used to drive in the plate bath composition into the passage ways of connected open pores in the foam matrix. The net result is to plate the inside surfaces of the pores in the foam matrix, while maintaining the passageways through the foam. Pretreatment of the pore surfaces can be used to promote adhesion of the metal. Particularly advantageous results are achieved when the foam matrix is a ceramic foam. | 05-19-2011 |
Simon Asaro, Concord CA
| Patent application number | Description | Published |
|---|---|---|
| 20100087562 | Polyurethane Foam Batt Insulation - Polyurethane foam materials are produced and used in batt form, and therefore are substitutes for insulation batts previously made of fibreglass insulation The polyurethane batts are preferably made of a flexible, and compressible foam material, such that the batts can be compressed and placed within a shipping container, and so that the compressed batt will form a friction fit in an opening, when in use An alternative insulation material and format are provided. | 04-08-2010 |