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Asao Yamashita, Fishkill US

Asao Yamashita, Fishkill, NY US

Patent application numberDescriptionPublished
20080217294METHOD AND SYSTEM FOR ETCHING A HAFNIUM CONTAINING MATERIAL - A method of etching a hafnium containing layer includes disposing a substrate having the hafnium containing layer in a plasma processing system, wherein a mask layer defining a pattern therein overlies the hafnium containing layer. A process gas including a HBr gas is introduced to the plasma processing system, and a plasma is formed from the process gas in the plasma processing system. The hafnium containing layer is exposed to the plasma in order to treat the hafnium containing layer. The hafnium containing layer is then wet etched using a dilute HF wet etch process.09-11-2008
20080311687Method and Apparatus for Optimizing a Gate Channel - The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.12-18-2008
20080311688Method and Apparatus for Creating a Gate Optimization Evaluation Library - The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.12-18-2008
20090081815Method and Apparatus for Spacer-Optimization (S-O) - The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.03-26-2009
20090082983Method and Apparatus for Creating a Spacer-Optimization (S-O) Library - The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.03-26-2009
20090242513Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models and Method for Using - The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.10-01-2009
20100036514Creating Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures - The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.02-11-2010
20100036518Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures - The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.02-11-2010
20100214545Creating Metal Gate Structures Using Lithography-Etch-Lithography-Etch (LELE) Processing Sequences - The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.08-26-2010

Patent applications by Asao Yamashita, Fishkill, NY US