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Asai, Kanagawa
Atsushi Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090105944 | DISPLAY ROUTE CREATION METHOD, DISPLAY ROUTE CREATION APPARATUS, AND DISPLAY ROUTE CREATION PROGRAM - A display route creation method includes: a route determination step in which a route determination section determines a route based on a departure point and a destination set on a map; a directional sign information extraction step in which a read section reads out directional sign information existing on the route from a map information storage section; and a route creation step in which a merging section merges a display image portion indicating the road direction included in the directional sign information and the route to create a display route in which the route and display image portion are integrated with each other. | 04-23-2009 |
| 20090241061 | Navigation apparatus, search result display method, and graphical user interface - A navigation apparatus includes: a basic frame generating unit for generating a basic frame two-dimensionally configured based on a search item axis and a search result display axis; a three-dimensional (3-D) search result listing image generating unit for generating a 3-D search result listing image in which a plurality of search result cards show as if they are stereoscopically arranged in a domino-like configuration along the search item axis and the search result display axis of the basic frame, the search result cards having titles of search results thereon; and a control unit for outputting the 3-D search result listing image to a predetermined display unit with a predetermined display angle, thereby displaying the 3-D search result listing image at the display angle. | 09-24-2009 |
| 20090259975 | LIST DISPLAY APPARATUS, LIST DISPLAY METHOD AND GRAPHICAL USER INTERFACE - A list display apparatus includes: a picture generating unit for generating a three-dimensional list picture, the three-dimensional list picture having a plurality of lower item cards having a respective lower items in a hierarchical structure being unfolded and expanded in a bellows configuration when shifting from an upper level to a lower level of the hierarchical structure, or the plurality of lower item cards being folded and collapsed in a bellows configuration when shifting from the lower level to the upper level of the hierarchical structure; and a control unit for outputting the three-dimensional list picture to a predetermined display unit, thereby displaying the three-dimensional list picture. | 10-15-2009 |
Ayumi Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110054041 | Oil-In-Water Type Cosmetic Emulsion - The invention provides an oil-in-water type cosmetic emulsion which can be applied to the skin without stickiness, and impart resilient and supple feel to the skin, while having good stability without causing viscosity decrease or separation even during a long-term storage. The oil-in-water type cosmetic emulsion comprises (a) a higher alcohol having 14 to 22 carbon atoms, (b) a hydrophilic polyoxyethylene alkyl ether, and (c) a glycerin monoalkyl ether, wherein alkyl moieties in (b) and (c) are linear saturated alkyl chains, and molar concentrations of (a) to (c) satisfy a relation [(b)+(c)]/(a)=0.1 to 1.0, and preferably satisfy a relation [(a)+(c)]/(b)=3 to 20. | 03-03-2011 |
Hideyoshi Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110040931 | MEMORY CONTROL METHOD AND DEVICE, MEMORY ACCESS CONTROL METHOD, COMPUTER PROGRAM, AND RECORDING MEDIUM - To dramatically increase the number of times data can be written into a flash memory. | 02-17-2011 |
Kiyoshi Asai, Kanagawa JP
Mao Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090287760 | COMMUNICATION TERMINAL, USER DATA TRANSFERRING SYSTEM AND USER DATA TRANSFERRING METHOD - A first communication terminal ( | 11-19-2009 |
Masaki Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110060952 | Semiconductor integrated circuit - The semiconductor integrated circuit including a memory macro includes a memory cell unit, input data holding units, and output data holding units. The input data holding units hold one of values of input data signals and a scan value depending on a scan control signal in accordance with an operating clock. The output data holding units hold one of values held by the input data holding units and data values stored by the memory cell unit depending on a test control signal in accordance with a phase different from a phase to operate the input data holding units. Further, the input data holding units and the output data holding units are alternately connected in series, and one input data holding unit is arranged at the top. A value held by one output data holding unit is transmitted to another input data holding unit arranged at a subsequent stage of the one output data holding units as the scan value. | 03-10-2011 |
| 20110113286 | SCAN TEST CIRCUIT AND SCAN TEST METHOD - A scan test circuit for a memory with a first memory cell column, a second memory cell column that replaces a failed column of the first memory cell column, a first switching circuit that connects one of the memory cell columns to a first peripheral circuit disposed at an input side, and a second switching circuit that connects one of the memory cell columns to a second peripheral circuit disposed at an output side, comprises: a test priority control circuit that controls the switching circuits to establish at least two patterns of connections of the memory cell columns to the peripheral circuits; and a test point circuit that includes scan flip-flop circuits employed in a scan test for detecting a delay fault of the peripheral circuits, and is disposed between the memory cell columns and the first switching circuit. | 05-12-2011 |
Nobuaki Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20100034515 | Information processing apparatus and method, and program - The present invention relates to an information processing apparatus and method, and a program which ensure that content can be played back. In a case where content and metadata necessary to play back the content are received from a content server via the Internet, a module dtSilk | 02-11-2010 |
| 20100293472 | Information processing apparatus and method, and program - The present invention relates to an information processing apparatus and method, and a program which ensure that content can be played back. In a case where content and metadata necessary to play back the content are received from a content server via the Internet, a module dtSilk | 11-18-2010 |
Nobutoshi Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20080219005 | LIGHT EMITTING DEVICE, DISPLAY DEVICE AND A METHOD OF MANUFACTURING DISPLAY DEVICE - Disclosed herein is a light emitting device, which includes a light emitting element configured to emit a light, and a concave mirror portion configured to reflect the light emitted from the light emitting element, the concave mirror portion being erected on a circumference of an emission surface of the light emitting element. The concave mirror portion has a light reflecting surface obtained by rotating a part of a parabola. A central axis of the rotation is set in a position of passing through a side of the parabola with respect to a middle point of a line segment joining the part of the parabola and a focal point of the parabola. | 09-11-2008 |
| 20100033089 | DISPLAY DEVICE - A display device includes: a light emitting layer configured to emit light in accordance with current; a first pixel separation film configured to define a first opening for providing a light emitting region when the light emitting layer emits light; and a second pixel separation film laminated on the first pixel separation film and configured to define a second opening that is restricted so as not to gradually become wider as apart from a surface contacted with the first pixel separation film. | 02-11-2010 |
| 20100245216 | Display panel and display device - A display panel includes: a plurality of pixel circuits formed in a matrix on a substrate; an insulating layer covering the plurality of pixel circuits; a plurality of light emitting elements connected to the plurality of pixel circuits, and arranged in a matrix on the insulating layer; a filtering layer including a light transmitting section at least in a part of a region facing the light emitting element and a light shielding section formed in a same plane as the light transmitting section, and formed on an opposite side from the pixel circuit in relation to the light emitting element; a light reflecting section formed in a region facing the light shielding section, and between the light emitting element and the filtering layer; and a light receiving element formed in a region facing the light shielding section, and on the pixel circuit side in relation to the light emitting element. | 09-30-2010 |
Nobuyuki Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110019512 | Optical disk reproducing device and optical disk recording and reproducing device - An optical disk reproducing device includes: a signal reproducing section configured to read and decode information recorded on an optical disk by an optical pickup unit, and reproduce the information, wherein the signal reproducing section includes a gain controlled amplifier circuit configured to amplify an radio frequency signal generated from a light receiving element, an automatic gain control circuit configured to control a gain of the gain controlled amplifier circuit, and a signal processing section configured to derive a part of an automatic gain control value generated in the automatic gain control circuit, and generate a control signal for adjusting one of an optical system path and a detection system path for controlling the optical pickup unit. | 01-27-2011 |
Satoru Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090308847 | EROSION PREVENTION METHOD AND MEMBER WITH EROSION PREVENTIVE SECTION - A method is provided, which ensures reliability during manufacture and in the use environment, and allows affording erosion prevention capability in an inexpensive manner, to an erosion-susceptible portion such as turbine rotor blades. An erosion preventive section | 12-17-2009 |
Shoujirou Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090300843 | POSTURAL CHANGE DEVICE OF MEDICAL DIAGNOSTIC APPARATUS - A postural change device used to allow imaging a plurality of postures while changing the posture of a portion to be examined of an object by means of a medical image diagnostic apparatus. | 12-10-2009 |
Shuji Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090078966 | Field-effect transistor, semiconductor chip and semiconductor device - A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact. | 03-26-2009 |
Tomoyuki Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110268894 | FLUORINE-CONTAINING LIQUID CRYSTAL COMPOUND, LIQUID CRYSTAL COMPOSITION, AND LIQUID CRYSTAL ELECTRO-OPTIC ELEMENT - A liquid crystal compound, a liquid crystal composition, and a liquid crystal electric optical device having a low rotational viscosity (γ1) and appropriate elastic constants. A fluorine-containing liquid crystal compound represented by formula (1). R | 11-03-2011 |
Tsuneaki Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090111126 | MAMMALIAN CELL-BASED IMMUNOGLOBULIN DISPLAY LIBRARIES - Disclosed are mammalian cell surface display vectors for isolating and/or characterizing immunoglobulins and various uses thereof. | 04-30-2009 |
| 20110008883 | MAMMALIAN CELL-BASED IMMUNOGLOBULIN DISPLAY LIBRARIES - Disclosed are mammalian cell surface display vectors for isolating and/or characterizing immunoglobulins and various uses thereof. | 01-13-2011 |
Yasuyuki Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20100304423 | CELL MEASURING VESSEL, EXTRACELLULAR POTENTIAL MEASURING METHOD, AND CHEMICAL TESTING METHOD - The cell observation using a conventional well plate takes much costs. Each well | 12-02-2010 |
Yoshihiko Asai, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090291514 | Process management method and process management data for semiconductor device - A process management method for managing manufacturing variability of an interconnection included in a semiconductor device is provided. The process management method includes: calculating interconnect resistance and interconnect capacitance regarding an interconnection included in the semiconductor device, under a condition that manufacturing variability of a width and a thickness of the interconnection is expressed by points on a predetermined circle of equal probability of a joint probability density function; and defining, based on the calculated interconnect resistance and interconnect capacitance, a variation range of interconnect resistance and interconnect capacitance caused by manufacturing variability. The variation range is defined two-dimensionally in a coordinate system where a first axis represents interconnect resistance and a second axis represents interconnect capacitance. | 11-26-2009 |
| 20100176820 | SENSITIVITY ANALYSIS SYSTEM AND SENSITIVITY ANALYSIS PROGRAM - A sensitivity analysis system has a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor device is stored. The interconnect structure has: a main interconnection; and a contact structure electrically connected to the main interconnection and extending toward a semiconductor substrate. Parameters contribute to parasitic capacitance of the interconnect structure, and variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. The sensitivity analysis system further has: a parameter setting unit that sets the variation to a plurality of conditions within the predetermined range; a capacitance calculation unit that calculates the parasitic capacitance of the interconnect structure in each of the plurality of conditions; and a sensitivity analysis unit that analyzes, based on the calculated parasitic capacitance, response of the parasitic capacitance to variation of the each parameter. | 07-15-2010 |
| 20100180241 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE AND DESIGN PROGRAM - A semiconductor device has an interconnect structure that includes a main interconnection and a contact structure. Parameters contributing to parasitic capacitance and interconnect resistance of the interconnect structure include: main parameters including width/thickness of the main interconnection; and sub parameter. Variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. A method of designing the semiconductor device includes: calculating the maximum capacitance value, the minimum capacitance value, the maximum resistance value and the minimum resistance value of the interconnect structure under a condition that respective variation amplitudes of the main parameters do not simultaneously take maximum values and variation of the sub parameter is fixed to a predetermined value; generating a CR-added netlist; and performing operation verification of the semiconductor device by using the CR-added netlist. | 07-15-2010 |