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| 20090157946 | MEMORY HAVING IMPROVED READ CAPABILITY - In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency. | 06-18-2009 |
| 20090219760 | MEMORY DEVICE HAVING READ CACHE - A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories. | 09-03-2009 |
| 20100088459 | Improved Hybrid Drive - A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks. The controller resets the identity of the most frequently read blocks in the volatile memory after a second period of time, where the second period of time is longer than said first period of time. | 04-08-2010 |
| 20100125444 | Method And Apparatus For Reducing Read Latency In A Pseudo Nor Device - A NOR emulating memory device has a memory controller with a first bus for receiving a NOR command signal, and for servicing a read operation from a desired address in a NOR memory. The memory controller has a second bus for communicating with a NAND memory in a NAND memory protocol, and a third bus for communicating with a RAM memory. A NAND memory is connected to the second bus. The NAND memory has an array of memory cells divided into a plurality of pages with each page divided into a plurality of sectors, with each sector having a plurality of bits. The NAND memory further has a page buffer for storing a page of bits read from the array during the read operation of the NAND memory. A RAM memory is connected to the third bus. The memory controller has a NOR memory for storing program code for initiating the operation of the memory controller, and for receiving NOR commands from the first bus and issuing NAND protocol commands on the second bus, in response thereto, to emulate the operation of a NOR memory device. The program code causes the memory controller to read a first sector of bits from the page buffer of the NAND memory and to write the sector of bits into the RAM memory, wherein the first sector contains the location of the desired address, and supplying data from said RAM memory in response to the read operation. | 05-20-2010 |
| 20100312926 | SWITCH FOR A TWO WAY CONNECTION BETWEEN A REMOVABLE CARD, A MOBILE WIRELESS COMMUNICATION DEVICE, OR A COMPUTER - A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The input of the first switch is connected to the first port. The input of the second switch is connected to the second port. The input of the third switch is connected to the third port. The first output of the first switch is connected to the second output of the second switch. The second output of the first switch is connected to the first output of the third switch. Finally, the first output of the second switch is connected to the second output of the third switch. | 12-09-2010 |
| 20110252185 | Method Of Operating A NAND Memory Controller To Minimize Read Latency Time - A NAND memory chip has a plurality of blocks with each block having a certain amount of storage and wherein the amount of storage in each block is the minimum amount that is erasable as a group. A controller controls the NAND memory chip. The method of operating the controller comprises writing data into a block of the NAND memory chip to partially fill the block. Then the controller tracks the extent to which the block has been written. After the block is partially written, the step is stopped. The controller determines if a request to the NAND memory chip needs to be serviced. The controller resumes the writing into the block after servicing the request. The present invention also relates to a method for controlling, the operation of a memory device having a controller for interfacing with and controlling a NAND memory. The memory device is responsive to either serial or parallel ATA protocol commands supplied from a host. | 10-13-2011 |
| 20110296080 | Method Of Writing To A NAND Memory Block Based File System With Log Based Buffering - A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation. | 12-01-2011 |
| 20110296276 | Dynamic Buffer Management In A NAND Memory Controller To Minimize Age Related Performance Degradation Due To Error Correction - An output buffer circuit for a non-volatile memory stores a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with the plurality of data bits. The output buffer circuit comprises an error check circuit for receiving the plurality of data bits and the plurality of ECC bits to determine if the plurality of data bits need to be corrected. The error check circuit supplies the plurality of data bits as its output, and generates a correction signal. An error correction circuit receives the plurality of data hits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. The output buffer circuit further has three or more storage circuits with each storage circuit having an input/output port. A bus connects to each of the storage circuits and to each other and supplies data bits between each storage circuit and between the nonvolatile memory and the storage circuits, and supplies data bits as the output of the output buffer circuit. A switch circuit is associated with each storage circuit for receiving the plurality of data bits; or the plurality of corrected data bits, and supplies same to the input/output port of the associated storage circuit and stores same as storage bits in the storage circuit, and supplies the storage bits as output of the storage circuit. | 12-01-2011 |
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| 20090109836 | METHOD AND SYSTEM FOR CONTROLLING REDUNDANCY OF INDIVIDUAL COMPONENTS OF A REMOTE FACILITY SYSTEM - A remote facility and method for operating the same includes a signal processing system including a primary multiplexer multiplexing IP signals to form a multiplexed signal, a primary modulator a primary transport processing system forming a transport stream signal from the multiplexed signal, a primary modulator modulating the transport stream signal to form a modulated signal, a backup multiplexer multiplexing IP signals to form the multiplexed signal, a backup modulator a primary transport processing system forming a transport stream signal from the multiplexed signal, a backup modulator modulating the transport stream signal to form a modulated signal. The remote facility includes a controller in communication with the primary multiplexer, the primary transport processing system, the primary modulator, the backup multiplexer, the backup transport processing system and the backup modulator, said controller forming an output signal using at least one of the primary multiplexer, the primary transport processing system, and the primary modulator and at least one of the backup multiplexer, the backup transport processing system and the backup modulator. The remote facility may be part of a television signal collection system that includes an IP network and a local collection facility in communication with the remote collection facility through the IP network. | 04-30-2009 |
| 20090109883 | METHOD AND SYSTEM FOR MONITORING AND ENCODING SIGNALS IN A LOCAL FACILITY AND COMMUNICATING THE SIGNALS BETWEEN A LOCAL COLLECTION FACILITY AND A REMOTE FACILITY USING AN IP NETWORK - A system and method for collecting signals includes an IP network, a remote facility and a local collection facility in communication with the local collection facility through the IP network. The local collection facility receives channel signals, encoding the channel signals into respective IP signals, communicating the respective IP signals through an IP network to the remote facility. The remote facility controls an antenna switch at the local collection facility to communicate a first channel signal of the channel signals to a monitoring receiver circuit module. The local collection facility generates a monitoring signal at the monitoring receiver circuit module and communicates the monitoring signal through to a remote facility through the IP network. | 04-30-2009 |
| 20090110052 | METHOD AND SYSTEM FOR MONITORING AND CONTROLLING A BACK-UP RECEIVER IN LOCAL COLLECTION FACILITY FROM A REMOTE FACILITY USING AN IP NETWORK - A system and method suitable for collecting local television signals includes a local collection facility having a plurality of primary receiver circuit modules with a first receiver circuit module and a back-up receiver module. The local collection facility includes the first receiver circuit module receiving and demodulating the first channel signal and forming a first IP signal. The first receiver has a first multicast group. The back-up receiver circuit module receives and demodulates the first channel signal and forming a second signal. The back-up receiver has a second multicast group. A remote facility is spaced apart from the local collection facility and communicates with the local collection facility through an IP backhaul. A primary decoder within the remote facility is communication with the IP backhaul and forms a decoded signal from the first IP signal. The primary decoder belongs to the first multi-cast group. A primary encoder within the remote facility communicates with the primary decoder and forms a first encoded signal from the decoded signal. A multiplexer multiplexes the first encoded signal into a multiplexed signal. A monitoring system includes commanding the primary decoder to join the second multicast group and discontinue the first multicast group. The primary decoder forms the decoded signal from the second IP signal. | 04-30-2009 |
| 20090113490 | METHOD AND SYSTEM FOR MONITORING AND CONTROLLING A LOCAL COLLECTION FACILITY FROM A REMOTE FACILITY THROUGH AN IP NETWORK - A method and system of collecting local television signals includes a local collection facility a plurality of primary receiver circuit modules comprising a first receiver circuit module. The first receiver circuit module receives and demodulates the first channel signal and forms an IP signal. A remote facility is spaced apart from the local collection facility and communicates with the local collection facility through an IP backhaul. A primary decoder within the remote facility is in communication with the IP backhaul and forms a decoded signal from the IP signal. A primary encoder within the remote facility in communication with the primary decoder forms a first encoded signal from the decoded signal. A multiplexer in the remote facility multiplexes the first encoded signal into a multiplexed signal. The multiplexed signal may provide an output signal used for uplinking or other type of distribution. | 04-30-2009 |
