| Patent application number | Description | Published |
|---|
| 20090321939 | Through Silicon via Bridge Interconnect - An integrated circuit bridge interconnect system includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die. | 12-31-2009 |
| 20100127937 | Antenna Integrated in a Semiconductor Chip - An antenna structure is integrated in a semiconductor chip. The antenna structure is formed by at least one of: a) one or more through-silicon vias (TSVs), and b) one or more crack stop structures. In certain embodiments, the antenna structure includes an antenna element formed by the TSVs. The antenna structure may further include a directional element formed by the crack stop structure. In certain other embodiments, the antenna structure includes an antenna element formed by the crack stop structure, and the antenna structure may further include a directional element formed by the TSVs. | 05-27-2010 |
| 20100148373 | Stacked Die Parallel Plate Capacitor - A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode. | 06-17-2010 |
| 20100200957 | Scribe-Line Through Silicon Vias - A semiconductor wafer includes dies to be scored from the semiconductor wafer. The semiconductor wafer also includes scribe-lines between the dies. Each scribe-line includes multiple through silicon vias. | 08-12-2010 |
| 20100283131 | Discontinuous Thin Semiconductor Wafer Surface Features - A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers. | 11-11-2010 |
| 20100283160 | Panelized Backside Processing for Thin Semiconductors - A semiconductor manufacturing method includes attaching a first die to a substrate panel. The method also includes applying a mold compound after attaching the first die to the substrate panel to the first die and the substrate panel. The method further includes thinning the first die and the mold compound after applying the mold compound. Attaching the die to the substrate panel before thinning eliminates usage of a carrier wafer when processing thin semiconductors. | 11-11-2010 |
| 20100313652 | Microfluidic Measuring Tool to Measure Through-Silicon Via Depth - A tool to measure the depth of one or more through-silicon vias, the tool fabricated in silicon to include a microfluidic chamber that is positioned over the one or more through-silicon vias, further including a fluid actuation chamber to inject fluid into the microfluidic chamber and into the one or more through-silicon vias, and a pressure sensing chamber to sense the fluid pressure to indicate when the one or more through-silicon vias are filled with the fluid. | 12-16-2010 |
| 20100314725 | Stress Balance Layer on Semiconductor Wafer Backside - A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die. | 12-16-2010 |
| 20110012239 | Barrier Layer On Polymer Passivation For Integrated Circuit Packaging - A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues. | 01-20-2011 |
| 20110037156 | Variable Feature Interface That Induces A Balanced Stress To Prevent Thin Die Warpage - A packaged semiconductor product includes a packaging substrate coupled to a semiconductor die through an interconnect structure with elements of variable features. The interconnect structure may be bumps or pillars. The variable features of the interconnect structure induce a reverse bend on the semiconductor die that mitigates warpage of the semiconductor die during semiconductor assembly by balancing bending of the packaging substrate during reflow. The variable features can be variable height and/or variable composition. | 02-17-2011 |
| 20110049694 | Semiconductor Wafer-To-Wafer Bonding For Dissimilar Semiconductor Dies And/Or Wafers - A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects and mold compound. When stacked, the die interconnects of the reconstituted wafer correspond to die interconnects on the second wafer. Wafer-to-wafer stacking improves throughput of the manufacturing process. The reconstituted wafer may include dies of different sizes than those in the second wafer. Also, the dies of the reconstituted wafer may be singulated from a wafer having a different size than the second wafer. Thus, this wafer-to-wafer manufacturing process may combine dies and/or wafers of dissimilar sizes. | 03-03-2011 |
| 20110075393 | Semiconductor Die-Based Packaging Interconnect - An electronic system includes a system board and a packaging substrate mounted on the system board. One or more semiconductor dies are mounted on the packaging substrate and coupled to the system board. The system also includes one or more semiconductor die-based packaging interconnects between the system board and the packaging substrate. The semiconductor die-based packaging interconnect has a first face coupled to the system board and a second face coupled to the packaging substrate. Through silicon vias located in the semiconductor die-based packaging interconnect enable communication between the system board and the one or more semiconductor dies. The semiconductor die-based packaging interconnects may include passive devices, active devices, and/or circuitry. For example, the semiconductor die-based packaging interconnect may provide impedance matching, decoupling capacitance, and/or amplifiers for minimizing insertion loss. | 03-31-2011 |
| 20110101347 | Interconnect Sensor for Detecting Delamination - An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination. | 05-05-2011 |
| 20110115064 | Hybrid Package Construction With Wire Bond And Through Silicon Vias - A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die. | 05-19-2011 |
