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Arvind
Arvind Bomdica, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080266009 | Ultra-low power crystal oscillator - An ultra-low power crystal oscillator architecture that draws less than 2 μA during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 μA. | 10-30-2008 |
| 20080284468 | METHOD AND APPARATUS FOR CONTROLLING A COMMUNICATION SIGNAL BY MONITORING ONE OR MORE VOLTAGE SOURCES - An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage. | 11-20-2008 |
| 20090167405 | Reduced Leakage Voltage Level Shifting Circuit - A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback. | 07-02-2009 |
| 20090168854 | De-Emphasis Circuit for a Voltage Mode Driver Used to Communicate Via a Differential Communication Link - A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage. | 07-02-2009 |
| 20100238598 | Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices - Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time. | 09-23-2010 |
| 20100238599 | Power Supply Equalization Circuit Using Distributed High-Voltage and Low-Voltage Shunt Circuits - Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail. | 09-23-2010 |
| 20110063010 | RECTIFYING AND LEVEL SHIFTING CIRCUIT - A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs. | 03-17-2011 |
| 20110133788 | DUAL FUNCTION VOLTAGE AND CURRENT MODE DIFFERENTIAL DRIVER - A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver. | 06-09-2011 |
| 20110148838 | BIAS CIRCUIT FOR A COMPLEMENTARY CURRENT MODE LOGIC DRIVE CIRCUIT - A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage. | 06-23-2011 |
Arvind Chandrasekraran, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090321126 | Concentric Vias In Electronic Substrate - A multiwall via structure in an electronic substrate having multiple conductive layers. The multiwall via structure includes an outer via coupled to a pair of the conductive layers, an inner via within the outer via and coupled to the same pair of conductive layers, and a dielectric layer between the inner and outer vias. In various embodiments, the pair of conductive layers can be inner conductive layers or outer conductive layers of the electronic substrate. In other embodiments, a method of preparing a multiwall via structure is provided. | 12-31-2009 |
Arvind Dangeti, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100223103 | DEAL MANAGEMENT IN A CUSTOMER RELATIONSHIP MANAGEMENT ENVIRONMENT - The present invention provides a method, system and computer-readable storage medium storing instructions for facilitating consistent application of price polices on every sales transaction supported through a customer relationship management system, in order to identify price exceptions in violation of stated corporate pricing objectives. Having such capabilities coupled with a customer relationship management system enables embodiments of the present invention to reduce the time to identify and evaluate price exceptions that impact revenue and margin. Agents responsible for sales interaction with customers can immediately identify violations of price policies. Those responsible for authorizing exceptions can easily determine the effect of those exceptions upon impacted markets. | 09-02-2010 |
Arvind Halliyal, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120038051 | BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME - A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect. | 02-16-2012 |
Arvind Jayasundar, Redmond, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20080225735 | REDUCING EFFECTS OF PACKET LOSS IN VIDEO TRANSMISSIONS - An error correction system determines a level of error correction protection to apply to a frame of video data to be transmitted by a sending endpoint to a receiving endpoint based on the predicted impact of packet loss as well as the importance of the frame based on inter-frame dependencies, frame size, packet loss probability, historical packet loss pattern, central processing unit (CPU) load, and available network bandwidth. At the receiving endpoint, when packet loss is detected for a particular frame, the receiving endpoint will attempt to recover the frame using protection packets received along with the video data. | 09-18-2008 |
Arvind Jugade, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20110306539 | PROCESS FOR MAKING PARTICLES FOR DELIVERY OF DRUG NANOPARTICLES - A process for making particles for delivery of drug nanoparticles is disclosed herein. The process comprises the steps of (a) forming a suspension of drug nanoparticles by mixing a precipitant solution with an anti-solvent solution under micro-mixing environment, where the formed nanoparticles have a narrow particle size distribution; (b) providing an excipient to at least one of the precipitant solution, the anti-solvent solution and the suspension of drug nanoparticles, the excipient being selected to maintain said drug nanoparticles in a dispersed state when in liquid form; and (c) drying the suspension of drug nanoparticles containing the excipient therein to remove solvent therefrom, wherein removal of the solvent causes the excipient to solidify and thereby form micro-sized matrix particles, each micro-sized particle being comprised of drug nanoparticles dispersed in a solid matrix of the excipient. | 12-15-2011 |
Arvind Kandhare, Gachibowli IN
| Patent application number | Description | Published |
|---|---|---|
| 20110161957 | Virtualized Eco-Friendly Remote Presentation Session Role - Systems, methods, and computer-readable storage media are disclosed for virtualized eco-friendly remote presentation session roles. In an embodiment, a connection broker monitors the servers of a server farm, and, based upon characteristics of remote presentation sessions served by VMs executing on those servers, directs VMs on those servers to be migrated between servers, changed from sleeping to running or vice versa, or other operations that may improve the performance of the server farm as a whole. | 06-30-2011 |
Arvind Kandhare, Hyderabad IN
| Patent application number | Description | Published |
|---|---|---|
| 20100318992 | TERMINAL SERVICES APPLICATION VIRTUALIZATION FOR COMPATABILITY - Systems, methods and computer-readable storage media are disclosed for providing a virtual single-user session to a client in a terminal server session. In an embodiment, requests to a resource in the system-space of a system made by an application are intercepted. A determination is made as to whether to virtualize the resource for the application. Where the resource is to be virtualized, a user-specific virtualized resource is created or maintained in user-space and provided to the application. | 12-16-2010 |
Arvind Keerti, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090251217 | AMPLIFIER DESIGN WITH BIASING AND POWER CONTROL ASPECTS - Techniques for biasing an amplifier using a replica circuit are disclosed. In an embodiment, a replica circuit having substantially the same topology and sizing as a push-pull amplifier circuit is coupled to a main push-pull amplifier circuit. A transistor in the replica circuit may be biased using feedback to generate a predetermined DC output voltage level, and such bias level may be applied to a corresponding transistor in the main push-pull amplifier circuit. In another embodiment, a transistor in a current bias module may be used to bias corresponding transistors in the main push-pull amplifier circuit and the replica circuit. Further techniques are disclosed for configuring the amplifier to have a non-uniform step size with finer resolution at lower power levels and coarser resolution at higher power levels to reduce power consumption at lower power levels. | 10-08-2009 |
| 20100026393 | DRIVER AMPLIFIER HAVING A PROGRAMMABLE OUTPUT IMPEDANCE ADJUSTMENT CIRCUIT - A driver amplifier in an integrated circuit is suitable for driving a signal onto an output node and through an output terminal, and through a matching network to a power amplifier. A novel Programmable Output Impedance Adjustment Circuit (POIAC) within the integrated circuit is coupled to the output node and affects an output impedance looking into the output terminal. When the output impedance would otherwise change (for example, due to a driver amplifier power gain change), the POIAC adjusts how it loads the output node such that the output impedance remains substantially constant. The POIAC uses a series-connected inductor and capacitor L-C-R circuit to load the output node, thereby reducing the amount of capacitance and die area required to perform multi-band impedance matching with a power amplifier. Multi-band operation is accomplished by changing an effective capacitance in the L-C-R circuit depending on communication band information received by the POIAC. | 02-04-2010 |
Arvind Krisnamurty US
| Patent application number | Description | Published |
|---|---|---|
| 20090122697 | INFORMATION PLANE FOR DETERMINING PERFORMANCE METRICS OF PATHS BETWEEN ARBITRARY END-HOSTS ON THE INTERNET - Performance metrics between any two arbitrary end-hosts are predicted based upon previous measurements on the Internet between a plurality of geographically dispersed vantage points and clusters of end-hosts. Each cluster comprises end-hosts that are related based upon their IP address prefixes. In response to a central agent that stores the measured data for each of a plurality of predicted paths on the Internet, the vantage points use traceroute software to measure and periodically update performance metrics such as latency, bottleneck capacity, bandwidth, and packet loss rate for links comprising the predicted paths between the vantage points and one (or more) destination points associated with each cluster, and gather such data using distributed application systems. A user or client application can subsequently request predicted performance metrics for communication between specific end-hosts, based upon the previous measurement data. | 05-14-2009 |
Arvind Mandhani, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090248928 | Integrating non-peripheral component interconnect (PCI) resources into a personal computer system - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 10-01-2009 |
| 20090249098 | Power management for a system on a chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 10-01-2009 |
| 20090300245 | Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 12-03-2009 |
| 20100287325 | INTEGRATING NON-PERIPHERAL COMPONENT INTERCONNECT (PCI) RESOURCES INTO A PERSONAL COMPUTER SYSTEM - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-11-2010 |
| 20110078356 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 03-31-2011 |
| 20110161542 | EMULATION OF AN INPUT/OUTPUT ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER - Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic. | 06-30-2011 |
| 20110271021 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-03-2011 |
| 20110320673 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 12-29-2011 |
Arvind Merwade, Karnataka IN
| Patent application number | Description | Published |
|---|---|---|
| 20100130541 | Processes for the preparation of clopidogrel - The invention relates to processes for the preparation of clopidogrel and salts thereof. The inventors have developed a process for preparing racemic clopidogrel by racemizing R(−) clopidogrel. The process includes the step of reacting R(−) clopidogrel with a powered anhydrous base in one or more solvents. | 05-27-2010 |
Arvind Parthasarathi, Belmont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110010349 | Method and device for users of enterprise software products to create, publish and share reviews of enterprise software products - We have invented a method and device for enabling users of enterprise software products to create, publish, and share reviews of enterprise software products. This useful, concrete and tangible result is accomplished through a server-hosted website accessible through the Internet. There are unique challenges with creating and sharing reviews of enterprise software products (compared to other products), and our invention solves these problems using several new and innovative methods we created, which form the basis of this application. Using this website, users of enterprise software can create a review of a product they are using or deploying, and also view reviews created by other users about the enterprise software products they are interested in. With usage, this invention becomes a global repository of enterprise software product reviews and a resource for users worldwide to share opinions and experiences to help each other evaluate, select, buy, and use enterprise software products. | 01-13-2011 |
Arvind Perumbala, Chennai IN
| Patent application number | Description | Published |
|---|---|---|
| 20090110278 | SYSTEM AND METHOD FOR VIEWING AND UTILIZING DATA FROM ELECTRONIC IMAGES - A method of utilizing data extracted from an electronic image includes receiving an electronic image associated with a subclient and receiving a plurality of data extracted from the electronic image and organized into predefined fields associated with the subclient. The method also includes displaying the electronic image in a first portion of a user interface and, in a second portion of the user interface, a field table containing the plurality of data and associated field names. | 04-30-2009 |
| 20090110279 | SYSTEM AND METHOD FOR EXTRACTING AND ORGANIZING DATA FROM ELECTRONIC IMAGES - A method of extracting and organizing data from electronic images includes processing a set of data fields representative of data to be extracted, mapping at least a subset of the set of data fields to at least one subclient, and attaching a rule from a set of rules to at least one of the mapped data fields. Each rule in the set of rules represents a transformation from a first data format to a preferred data format. The method also includes extracting data from at least one electronic image for the at least one subclient into the plurality of mapped data fields using the attached rule and storing the extracted data. | 04-30-2009 |
Arvind Saklani, Mumbai IN
| Patent application number | Description | Published |
|---|---|---|
| 20110177180 | HERBAL COMPOSITION AND METHOD FOR THE TREATMENT OF VIRAL INFECTION - The present invention relates to a herbal composition comprising extract of the plant | 07-21-2011 |
Arvind Saraf, Surat IN
| Patent application number | Description | Published |
|---|---|---|
| 20090089169 | Event Based Serving - Apparatus, system and methods for an event based advertising server are enclosed. Trend data measured over time periods for user queries are measured. A determination is made as to whether an eligibility event for an advertisement has occurred. If an eligibility event is determined to have occurred, eligibility change data for the advertisement is generated. The eligibility change data defines a change to the presentation eligibility of the advertisement and is based on the trend data. | 04-02-2009 |
| 20110274373 | Digital Image Archiving and Retrieval in a Mobile Device System - A computer-implemented method of managing information is disclosed. The method can include receiving a message from a mobile device configured to connect to a mobile device network (the message including a digital image taken by the mobile device and including information corresponding to words), determining the words from the digital image information using optical character recognition, indexing the digital image based on the words, and storing the digital image for later retrieval of the digital image based on one or more received search terms. | 11-10-2011 |
Arvind Sathi, Englewood, CO US
| Patent application number | Description | Published |
|---|---|---|
| 20090132419 | OBFUSCATING SENSITIVE DATA WHILE PRESERVING DATA USABILITY - A method and system for obfuscating sensitive data while preserving data usability. The in-scope data files of an application are identified. The in-scope data files include sensitive data that must be masked to preserve its confidentiality. Data definitions are collected. Primary sensitive data fields are identified. Data names for the primary sensitive data fields are normalized. The primary sensitive data fields are classified according to sensitivity. Appropriate masking methods are selected from a pre-defined set to be applied to each data element based on rules exercised on the data. The data being masked is profiled to detect invalid data. Masking software is developed and input considerations are applied. The selected masking method is executed and operational and functional validation is performed. | 05-21-2009 |
| 20090132575 | MASKING RELATED SENSITIVE DATA IN GROUPS - A method and system of masking a group of related data values. A record in an unmasked data file of n records is read. The record includes a first set of data values of data elements included in a related data group (RDG) and one or more data values of one or more data elements external to the RDG. A random number k is received. A second set of data values is retrieved from a lookup table that associates n key values with n sets of data values. Retrieving the second set of data values includes identifying that the second set of data values is associated with a key value of k. The n sets of data values are included in the umnasked data file's n records. The record is masked by replacing the first set of data values with the retrieved second set of data values. | 05-21-2009 |
Arvind Sawinathan, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110195714 | METHODS AND APPARATUS FOR PERFORMING REGISTRATION ACROSS RADIO ACCESS TECHNOLOGIES - Methods and apparatuses are provided that facilitate balancing cross-domain paging with registrations performed by a device moving between multiple networks. A device communicating in idle-mode with one or more base stations can obtain one or more parameters regarding a base station using a radio access technology (RAT) to control whether the device performs registration on a network of a different RAT. Thus, the device moving from an area of coverage from one base station of the RAT to a different area that includes coverage from another base station of the different RAT (or vice versa) can determine whether and/or when to perform a registration on the network of the different RAT for receiving paging signals related to the different RAT based at least in part on the one or more parameters. | 08-11-2011 |
Arvind Shah, Berax CH
| Patent application number | Description | Published |
|---|---|---|
| 20100024865 | CONTINUOUS COATING INSTALLATION, METHODS FOR PRODUCING CRYSTALLINE SOLAR CELLS, AND SOLAR CELL - A continuous coating installation is disclosed. The installation includes a vacuum chamber having a supply opening for supplying a substrate to be coated and a discharge opening for discharging the coated substrate. The installation also includes a physical vapour deposition device for coating a surface of the substrate, and a laser crystallization system for simultaneously illuminating at least one sub-partial area of a currently coated partial area of the surface of the substrate with at least one laser beam. The installation further includes a transport device for transporting the substrate in a feedthrough direction from the supply opening to the discharge opening and for continuously or discontinuously moving the substrate during the coating thereof in the feedthrough direction. | 02-04-2010 |
Arvind Sharma, Bayern DE
| Patent application number | Description | Published |
|---|---|---|
| 20080311905 | Call Routing in a Mobile Communication System - A method and a system for handling a mobile terminating call in a mobile communications network, wherein interrogation ( | 12-18-2008 |
Arvind Sharma, Eindhoven NL
| Patent application number | Description | Published |
|---|---|---|
| 20090005037 | Intelligent Network Services - A method and control node ( | 01-01-2009 |
Arvind Srinivasamoorthy, Hyderabad IN
| Patent application number | Description | Published |
|---|---|---|
| 20110161913 | TECHNIQUES FOR MANAGING FUNCTIONAL SERVICE DEFINITIONS IN AN SOA DEVELOPMENT LIFECYCLE - A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables. | 06-30-2011 |
| 20110161914 | TECHNIQUES FOR AUTOMATED GENERATION OF DEPLOYMENT PLANS IN AN SOA DEVELOPMENT LIFECYCLE - A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables. | 06-30-2011 |
| 20110161915 | TECHNIQUES FOR RAPID DEPLOYMENT OF SERVICE ARTIFACTS - A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables. | 06-30-2011 |
| 20110161921 | TECHNIQUES FOR AUTOMATED GENERATION OF SERVICE ARTIFACTS - A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables. | 06-30-2011 |
Arvind Viswanathan, Vancouver CA
| Patent application number | Description | Published |
|---|---|---|
| 20090064105 | ACCESSING A ERP APPLICATION OVER THE INTERNET USING STRONGLY TYPED DECLARATIVE LANGUAGE FILES - A method of converting ERP data in a database managed by an ERP application and accessed through an ERP API and ERP Message Agent API (MAAPI) to strongly typed data in Java objects includes steps of reading, parsing, creating, and populating. A XML file containing the definition of the Java objects and their attributes of HyperText Markup Language (HTML) statements which specifies presentation format is read. Each of the declarations and HTML statements are parsed to identify definitions of objects and their attributes. The respective objects are created with their attributes. The objects are populated with data from the ERP data. | 03-05-2009 |