| Patent application number | Description | Published |
|---|
| 20080288750 | Small barrier with local spinning - A barrier with local spinning. The barrier is described as a barrier object having a bit vector embedded as a pointer. If the vector bit is zero, the object functions as a counter; if the vector bit is one, the object operates as a pointer to a stack. The object includes the total number of threads required to rendezvous at the barrier to trigger release of the threads. The object points to a stack block list that describes each thread that has arrived at the barrier. Arriving at the barrier involves reading the top stack block, pushing onto the list a stack block for the thread that just arrived, decrementing the thread count, and spinning on corresponding local memory locations or timing out and blocking. When the last thread arrives at the barrier, the barrier is reset and all threads at the barrier are awakened for the start of the next process. | 11-20-2008 |
| 20090187784 | FAIR AND DYNAMIC CENTRAL PROCESSING UNIT SCHEDULING - Embodiments that facilitate the fair and dynamic distribution of central processing unit (CPU) time are disclosed. In accordance with one embodiment, a method includes organizing one or more processes into one or more groups. The method further includes allocating a CPU time interval for each group. The allocation of a CPU time interval for each group is accomplished by equally distributing a CPU cycle based on the number of groups. The method also includes adjusting the allocated CPU time intervals based on a change in the quantity of the one or more groups. | 07-23-2009 |
| 20090249094 | POWER-AWARE THREAD SCHEDULING AND DYNAMIC USE OF PROCESSORS - Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy. | 10-01-2009 |
| 20100017581 | LOW OVERHEAD ATOMIC MEMORY OPERATIONS - Embodiments that provide low-overhead restricted memory transactions are disclosed. In accordance with one embodiment, the method includes providing one or more references to processor-specific data that corresponds to a first processor. The method further includes detecting an interrupt to the first processor when the interrupt indicates modification of the one or more references to the processor-specific data during the execution of one or more instructions. The method also includes taking remedial action on the one or more instructions when the interrupt is detected. | 01-21-2010 |
| 20100083261 | INTELLIGENT CONTEXT MIGRATION FOR USER MODE SCHEDULING - Embodiments for performing directed switches between user mode schedulable (UMS) thread and primary threads are disclosed. In accordance with one embodiment, a primary thread user portion is switched to a UMS thread user portion so that the UMS thread user portion is executed in user mode via the primary thread user portion. The primary thread is then transferred into kernel mode via an implicit switch. A kernel portion of the UMS thread is then executed in kernel mode using the context information of a primary thread kernel portion. | 04-01-2010 |
| 20100083275 | TRANSPARENT USER MODE SCHEDULING ON TRADITIONAL THREADING SYSTEMS - Embodiments for performing cooperative user mode scheduling between user mode schedulable (UMS) threads and primary threads are disclosed. In accordance with one embodiment, an asynchronous procedure call (APC) is received on a kernel portion of a user mode schedulable (UMS) thread. The status of the UMS thread as it is being processed in a multi-processor environment is determined. Based on the determined status, the APC is processed on the UMS thread. | 04-01-2010 |
| 20100251250 | LOCK-FREE SCHEDULER WITH PRIORITY SUPPORT - Techniques for implementing a lock-free scheduler with ordering support are described herein. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects of the present disclosure; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. | 09-30-2010 |
| 20110307730 | Power-Aware Thread Scheduling and Dynamic Use of Processors - Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy. | 12-15-2011 |
