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Arsintescu

Bogdan Arsintescu, Santa Clara, CA US

Patent application numberDescriptionPublished
20080282212SYSTEM AND METHOD ENABLING CIRCUIT TOPOLOGY RECOGNITION WITH AUTO-INTERACTIVE CONSTRAINT APPLICATION AND SMART CHECKING - A computer implemented method is provided for interactive application of constraints to sub-circuits in a circuit design stored in a computer readable medium, comprising: receiving from a first designer a selection of a sub-circuit; receiving from the first designer a constraint; producing an information structure in computer readable medium that associates a graph representing a topology of the selected sub-circuit with the received constraint; using the graph to identify sub-circuit instances in the circuit design having the same topology as the selected sub-circuit; receiving from a second designer a selection of the information structure; presenting to the second designer one or more of the identified sub-circuit instances and the received constraint; and receiving from the second designer instruction as to application of the received constraint to one or more of the presented sub-circuit instances.11-13-2008

Bogdan G. Arsintescu, San Jose, CA US

Patent application numberDescriptionPublished
20110066995ANNOTATION MANAGEMENT FOR HIERARCHICAL DESIGNS OF INTEGRATED CIRCUITS - A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media.03-17-2011

Bogdan George Arsintescu, San Jose, CA US

Patent application numberDescriptionPublished
20090282379SYSTEM AND METHOD FOR CIRCUIT SCHEMATIC GENERATION - The present invention provides a system and method for generating circuit schematic that includes extracting connectivity data of a plurality of devices from a netlist, categorizing the plurality of devices into groups, placing Schematic Analog Placement Constraints on all the instances by identifying instances among the groups that match with a circuit template (in-built as well as user-specified), creating a BFS instance tree of tree instances, creating a two terminal device clusters and creating instance attachments. Using the constraints during grid based placement and eventually generated schematic which look like analog schematic.11-12-2009

George B. Arsintescu, San Jose, CA US

Patent application numberDescriptionPublished
20090077505GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects.03-19-2009
20090077513GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects.03-19-2009
20100325597GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects.12-23-2010

Patent applications by George B. Arsintescu, San Jose, CA US