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Arora, Bangalore
Manoj K. Arora, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20120047333 | EXTENDING A CACHE COHERENCY SNOOP BROADCAST PROTOCOL WITH DIRECTORY INFORMATION - In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed. | 02-23-2012 |
Praveen Arora, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100107151 | METHOD AND SYSTEM FOR IMPLEMENTING PERFORMANCE KITS - Described is an improved method, system, and computer program product for implementing performance kits. Test data for the performance kit is preloaded into an installation image that is distributed with a vendor's product. This avoids the need for the customer himself to have to perform the tasks of installing the test data at the customer site. | 04-29-2010 |
Rishi Arora, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100114926 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING AUTOMATED WORKLISTS - A method, system, and computer program product for implementing automated worklists are provided. The method includes generating a worklist, which further includes retrieving a worklist template corresponding to the worklist and, via a first query, selecting a listing of members and attributes to be populated in the worklist, the attributes include a status indicator of an action item specified for each of the members of the worklist. The worklist generation also includes building a worklist member table with results of the first query and, via a second query, and using attributes of the worklist member table, identifying up-to-date values of one or more worklist member attributes, and outputting results of the second query to the worklist. The method also includes presenting the worklist to a corresponding assignee. For each of the members in the worklist, the status indicator is editable to update a status of the member. | 05-06-2010 |
Sampan Arora, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090024876 | System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation - A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly. | 01-22-2009 |
| 20090024886 | System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation - A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution. | 01-22-2009 |
| 20090024894 | SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE - During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address. | 01-22-2009 |
| 20090070629 | System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation - A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes. | 03-12-2009 |
| 20090070631 | System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation - A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor. | 03-12-2009 |
Satish Arora, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100322415 | MULTILAYER ENCRYPTION OF A TRANSPORT STREAM DATA AND MODIFICATION OF A TRANSPORT HEADER - Several methods and a system of multilayer encryption of a transport stream data and modification of a transport header are disclosed. An exemplary embodiment provides a method of a multilayer encryption. The method includes further encrypting an initially encrypted transport stream data to generate a multilayer encrypted data using a processor and a memory. The method also includes determining a further encryption flag data. The encryption method modifies a transport header of the multilayer encrypted data. In addition, the encryption method includes the further encryption flag data in an adapted component of a modified transport header. | 12-23-2010 |
Silky Arora, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20110055797 | AUTOMATIC MONITOR GENERATION FROM QUANTITATIVE SCENARIO BASED REQUIREMENT SPECIFICATIONS - A method for validating a design model includes generating a requirement in the form of an event sequence chart with quantitative constraints and generating a monitor from the event sequence chart, wherein the monitor is configured to validate the design model with respect to the requirement. | 03-03-2011 |
Vikram J. Arora, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20080320552 | ARCHITECTURE AND SYSTEM FOR ENTERPRISE THREAT MANAGEMENT - Enterprise threat assessment and management provides both physical and logical security. Physical access control systems are configured to identify physical events in the physical domain, and logical access control systems are configured to identify logical events in the logical domain. Connectors establish uninterrupted coupling to the physical and logical access control systems. Event middleware is configured to selectively subscribe only to those events that correspond to defined policies. The policies define a correlation of the physical and logical events, actions are initiated depending upon the correlated physical and logical events defined by the policies. | 12-25-2008 |
| 20090216587 | MAPPING OF PHYSICAL AND LOGICAL COORDINATES OF USERS WITH THAT OF THE NETWORK ELEMENTS - Physical coordinates of a user and an asset are determined. A probability that the user and the asset are close to one another is determined based on the physical coordinates of the user and the asset. Permission for the user to access to the asset is decided based on the probability. Additionally or alternatively, logical coordinates of a user and an asset are determined. The logical coordinates of the user and the asset are compared, and permission for the user to access to the asset is decided based on the comparison. | 08-27-2009 |