| Patent application number | Description | Published |
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| 20110040651 | SYSTEMS AND METHODS FOR MANAGING ORDERS MADE VIA A COMPUTER NETWORK - A system and method for allowing a user to schedule pickup of an ordered item provides a user interface having user interface elements for allowing a user to specify a frequency with which an order is it to be picked up, for informing a user as to availability of the item for pickup, and/or for allowing a user to request that an item be held in reserve for pickup within a given period of time, such as 24 hours. Frequency options provided to the user for selection when scheduling an order for pickup may include a one-time frequency, a daily frequency, a weekly frequency, a monthly frequency, and user specified dates. The information as to availability of the item for pickup is determined considering a time of order and real-time stocking information for the item. | 02-17-2011 |
| 20110320309 | SYSTEMS AND METHODS FOR MANAGING ORDERS MADE VIA A COMPUTER NETWORK - A system and method for allowing a user to schedule pickup of an ordered item provides a user interface having user interface elements for allowing a user to specify a frequency with which an order is it to be picked up, for informing a user as to availability of the item for pickup, and/or for allowing a user to request that an item be held in reserve for pickup within a given period of time, such as 24 hours. Frequency options provided to the user for selection when scheduling an order for pickup may include a one-time frequency, a daily frequency, a weekly frequency, a monthly frequency, and user specified dates. The information as to availability of the item for pickup is determined considering a time of order and real-time stocking information for the item. | 12-29-2011 |
| Patent application number | Description | Published |
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| 20090144491 | METHOD AND SYSTEM FOR IMPLEMENTING PRIORITIZED REFRESH OF DRAM BASED CACHE - A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set; wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache. | 06-04-2009 |
| 20090144492 | STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE - A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache. | 06-04-2009 |
| 20090144503 | METHOD AND SYSTEM FOR INTEGRATING SRAM AND DRAM ARCHITECTURE IN SET ASSOCIATIVE CACHE - A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request. | 06-04-2009 |
| 20090144506 | METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE - A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache. | 06-04-2009 |
| 20090193187 | DESIGN STRUCTURE FOR AN EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES - A design structure for an embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful. | 07-30-2009 |
