Patent application number | Description | Published |
20080259004 | PASSIVE MATRIX ELECTRO-LUMINESCENT DISPLAY SYSTEM - A passive matrix, electro-luminescent display system has a passive matrix, electro-luminescent display having an orthogonally oriented array of column and row electrodes and an electro-luminescent layer located between the electrodes at the intersection of each column and row electrode forming an individual light-emitting element. Drivers provide separate signals at different times to different groups of row electrodes within the array of row electrodes; wherein the row electrodes of each group simultaneously receive at least two different level signals. A display driver receives and processes the input image signal to provide a presharpened image control signal. Column drivers respond to the presharpened image control signal for simultaneously providing a signal to the multiple column electrodes within the array of column electrodes at the same time signals are provided to the groups of row electrodes so that the concurrence of row and column signals causes individual light-emitting element to produce light. | 10-23-2008 |
20090021455 | REDUCED POWER CONSUMPTION IN OLED DISPLAY SYSTEM - A method of controlling a passive matrix display having rows and columns of pixels including receiving an input image signal; determining drive signals for at least a first image field and a second image field; calculating a value that is correlated to a change in the total capacitive charge of the pixels that will occur between the display of the first image field and the second image field for at least one column of the passive-matrix, electro-luminescent display; adjusting at least one of the drive signals within first or second image fields to compensate for the change in total capacitive charge; and providing adjusted drive signals for each pixel. | 01-22-2009 |
20090073079 | TILED PASSIVE MATRIX ELECTRO-LUMINESCENT DISPLAY - A tiled, passive-matrix, EL display, including two or more EL tiles, each EL tile including an array of rows and columns of light-emitting elements, each light-emitting element being formed from a light-emitting layer that is sandwiched between an orthogonal array of row and column electrodes wherein each of the two or more EL tiles further include at least one row driver; at least one column driver for operating in conjunction with each of the at least one row drivers to control the flow of electrons between the row and column electrodes to control the emission of light from each of the light-emitting elements, with a first exception that when the boundary between the two tiles is to be illuminated, then the number of rows of simultaneously illuminated rows of light-emitting elements within one tile is less than the predetermined number. | 03-19-2009 |
20100219429 | TOP-EMITTING OLED DEVICE WITH LIGHT-SCATTERING LAYER AND COLOR-CONVERSION - A top-emitting OLED device, comprising: one or more OLEDs formed on a substrate; a light-scattering layer formed over the one or more OLEDs; a transparent cover; one or more color filters formed on the transparent cover; a color-conversion material layer formed over the color filters, or formed over or integral with the light-scattering layer; wherein the substrate is aligned and affixed to the transparent cover so that the locations of the color filters and color conversion material correspond to the location of the OLEDs, and the color-conversion material layer, color filters, and the light-scattering layer are between the cover and substrate, and a low-index gap is formed between the light-scattering layer and the color filters, with no light-scattering layer being positioned between the color conversion material layer and the low-index gap, wherein the color-conversion material layer is formed integrally with the light-scattering layer. | 09-02-2010 |
20110248256 | TOP-EMITTING OLED DEVICE WITH LIGHTS-SCATTERING LAYER AND COLOR-CONVERSION - A top-emitting OLED device, comprising: one or more OLEDs formed on a substrate; a light-scattering layer formed over the one or more OLEDs; a transparent cover; one or more color filters formed on the transparent cover; a color-conversion material layer formed over the color filters, or formed over or integral with the light-scattering layer; wherein the substrate is aligned and affixed to the transparent cover so that the locations of the color filters and color conversion material correspond to the location of the OLEDs, and the color-conversion material layer, color filters, and the light-scattering layer are between the cover and substrate, and a low-index gap is formed between the light-scattering layer and the color filters, with no light-scattering layer being positioned between the color conversion material layer and the low-index gap, wherein the color-conversion material layer is formed integrally with the light-scattering layer. | 10-13-2011 |
Patent application number | Description | Published |
20090072401 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER - Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure. | 03-19-2009 |
20090075472 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 03-19-2009 |
20100187579 | TRANSISTOR DEVICES AND METHODS OF MAKING - In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers. | 07-29-2010 |
20110204523 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 08-25-2011 |
20120061684 | TRANSISTOR DEVICES AND METHODS OF MAKING - In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers. | 03-15-2012 |
20120126358 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH - A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 05-24-2012 |
20120198403 | MANUFACTURING FEATURES OF DIFFERENT DEPTH BY PLACEMENT OF VIAS - A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process. | 08-02-2012 |
20120329269 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 12-27-2012 |
20120329272 | METHOD FOR FORMING SMALL DIMENSION OPENINGS IN THE ORGANIC MASKING LAYER OF TRI-LAYER LITHOGRAPHY - A method for forming small dimension openings in the organic masking layer of tri-layer lithography. The method includes forming an organic polymer layer over a semiconductor substrate; forming a silicon containing antireflective coating on the organic polymer layer; forming a patterned photoresist layer on the antireflective coating, the patterned photoresist layer having an opening therein; performing a first reactive ion etch to transfer the pattern of the opening into the antireflective coating to form a trench in the antireflective coating, the organic polymer layer exposed in a bottom of the trench; and performing a second reactive ion etch to extend the trench into the organic polymer layer, the second reactive ion etch forming a polymer layer on sidewalls of the trench, the second reactive ion etch containing a species derived from a gaseous hydrocarbon. | 12-27-2012 |
20130001749 | FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION - A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask. | 01-03-2013 |
20130001750 | FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION - A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask. | 01-03-2013 |
20130026639 | Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 01-31-2013 |
20130175658 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH FOR SEMICONDUCTOR DEVICE FORMATION - A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 07-11-2013 |
20130216776 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 08-22-2013 |
20140110846 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 04-24-2014 |
Patent application number | Description | Published |
20090020739 | Method for Delineation of Phase Change Memory Cell Via Film Resistivity Modification - A PCM cell structure comprises a lower electrode composed of a Phase Change Memory (PCM) layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical isolation between adjacent cells is provided by modifying the conductivity of the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition. | 01-22-2009 |
20090176040 | Methods of Forming Tubular Objects - A tubular object is fabricated by a method comprising the steps of providing a first layer, forming a second layer on the first layer, and then patterning the second layer to form a raised feature with one or more sidewalls. Subsequently, the first layer is processed such that components of the first layer deposit on the one or more sidewalls of the raised feature. | 07-09-2009 |
20090176062 | Methods of Forming Features in Integrated Circuits - A feature is formed in an integrated circuit by providing one or more layers to be patterned, providing a first layer overlying the one or more layers to be patterned, and providing a second layer overlying the first layer. The second layer is patterned to form a raised feature with one or more sidewalls. Subsequently, the first layer is processed such that components of the first layer deposit on the one or more sidewalls of the raised feature to form a mask. The mask is used to pattern the one or more layers to be patterned. | 07-09-2009 |
20100001253 | Method for delineation of phase change memory cell via film resistivity modification - A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power. | 01-07-2010 |
20120302057 | SELF ALIGNING VIA PATTERNING - A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch. | 11-29-2012 |
Patent application number | Description | Published |
20120295874 | COFERONS AND METHODS OF MAKING AND USING THEM - The present invention is directed to a monomer useful in preparing therapeutic compounds. The monomer includes one or more pharmacophores which potentially binds to a target molecule with a dissociation constant of less than 300 μM and a linker element connected to the pharmacophore. The linker element has a molecular weight less than 500 daltons, is connected, directly or indirectly through a connector, to the pharmacophore. | 11-22-2012 |
20130123284 | HETEROCYCLIC COMPOUNDS USEFUL FOR KINASE INHIBITION - Provided herein are compounds useful for kinase inhibition. | 05-16-2013 |
20140161729 | COFLUORONS AND METHODS OF MAKING AND USING THEM - The present invention is directed to method of using a collection of monomers capable of forming multimers as a fluorescence reporter in different applications such as ligand detection/screening, disease diagnosis, drug discovery or screening, fluorescent labeling and imaging, or other fluorescent methodologies. Each monomer in the collection includes one or more ligand elements useful for binding to a target molecule with a dissociation constant of less than 300 μM and a linker element connected to the ligand elements directly or indirectly through a connector. Association of linker elements of different combinations of monomers, with their ligand elements bound to the target molecule to form a multimer, will generate a unique fluorescent signature different from that produced by those monomers either alone or in association with each other in the absence of the target molecule, when subjected to electromagnetic excitement. | 06-12-2014 |
20140163229 | SILYL MONOMERS CAPABLE OF MULTIMERIZING IN AN AQUEOUS SOLUTION, AND METHODS OF USING SAME - Described herein are silyl monomers capable of forming a biologically useful multimer when in contact with one, two, three or more other monomers in an aqueous media. Such multimer forming associations of monomers may be promoted by the proximal binding of the monomers to their target biomolecule(s). In one aspect, such monomers may be capable of binding to another monomer in an aqueous media (e.g. in vivo) to form a multimer, (e.g. a dimer). Contemplated monomers may include a ligand moiety, a linker element, and a connector element that joins the ligand moiety and the linker element. In an aqueous media, such contemplated monomers may join together via each linker element and may thus be capable of modulating one or more biomolecules substantially simultaneously, e.g., modulate two or more binding domains on a protein or on different proteins. | 06-12-2014 |
20140194383 | MONOMERS CAPABLE OF DIMERIZING IN AN AQUEOUS SOLUTION, AND METHODS OF USING SAME - Described herein are monomers capable of forming a biologically useful multimer when in contact with one, two, three or more other monomers in an aqueous media. In one aspect, such monomers may be capable of binding to another monomer in an aqueous media (e.g. in vivo) to form a multimer, (e.g. a dimer). Contemplated monomers may include a ligand moiety, a linker element, and a connector element that joins the ligand moiety and the linker element. In an aqueous media, such contemplated monomers may join together via each linker element and may thus be capable of modulating one or more biomolecules substantially simultaneously, e.g., modulate two or more binding domains on a protein or on different proteins. | 07-10-2014 |
20140296268 | THERAPEUTIC METHODS AND COMPOSITIONS INVOLVING ALLOSTERIC KINASE INHIBITION - The present invention is directed to methods and compositions for suppressing lymphangiogenesis, angiogenesis and/or tumor growth. The methods comprise contacting the tumor with a compound that (i) stabilizes a protein kinase in the inactive state and (ii) is not an ATP competitive inhibitor of the protein kinase in the active state. | 10-02-2014 |
20150158828 | Heterocyclic Compounds Useful for Kinase Inhibition - Provided herein are compounds useful for kinase inhibition. | 06-11-2015 |
Patent application number | Description | Published |
20140243286 | BROMODOMAIN LIGANDS CAPABLE OF DIMERIZING IN AN AQUEOUS SOLUTION, AND METHODS OF USING SAME - Described herein are monomers capable of forming a biologically useful multimer when in contact with one, two, three or more other monomers in an aqueous media. In one aspect, such monomers may be capable of binding to another monomer in an aqueous media (e.g. in vivo) to form a multimer (e.g. a dimer). Contemplated monomers may include a ligand moiety, a linker element, and a connector element that joins the ligand moiety and the linker element. In an aqueous media, such contemplated monomers may join together via each linker element and may thus be capable of modulating one or more biomolecules substantially simultaneously, e.g., modulate two or more binding domains on a protein or on different proteins. | 08-28-2014 |
20140243321 | BIOORTHOGONAL MONOMERS CAPABLE OF DIMERIZING AND TARGETING BROMODOMAINS, AND METHODS OF USING SAME - Described herein are monomers capable of forming a biologically useful multimer when in contact with one, two, three or more other monomers in an aqueous media. In one aspect, such monomers may be capable of binding to another monomer in an aqueous media (e.g. in vivo) to form a multimer, (e.g. a dimer). Contemplated monomers may include a ligand moiety, a linker element, and a connector element that joins the ligand moiety and the linker element. In an aqueous media, such contemplated monomers may join together via each linker element and may thus be capable of modulating one or more biomolecules substantially simultaneously, e.g., modulate two or more binding domains on a protein or on different proteins. | 08-28-2014 |
20140243322 | BIVALENT BROMODOMAIN LIGANDS, AND METHODS OF USING SAME - Described herein are compounds capable of modulating one or more biomolecules substantially simultaneously, e.g., modulating two or more binding domains (e.g., bromodomains) on a protein or on different proteins. | 08-28-2014 |
20140296181 | METHODS OF MODULATING ONCOGENIC FUSION PROTEINS - Described herein, at least in part, are methods of modulating oncogenic fusion proteins. | 10-02-2014 |
20150080570 | ALPHA,BETA-UNSATURATED MONOMERS CAPABLE OF MULTIMERIZATION IN AN AQUEOUS SOLUTION, AND METHODS OF USING SAME - Described herein are monomers capable of forming a biologically useful multimer when in contact with one, two, three or more other monomers in an aqueous media. In one aspect, such monomers may be capable of binding to another monomer in an aqueous media (e.g. in vivo) to form a multimer, (e.g. a dimer). Contemplated monomers may include a ligand moiety, a linker element, and a connector element that joins the ligand moiety and the linker element. In an aqueous media, such contemplated monomers may join together via each linker element and may thus be capable of modulating one or more biomolecules substantially simultaneously, e.g., modulate two or more binding domains on a protein or on different proteins. | 03-19-2015 |
20150087043 | MONOMERS CAPABLE OF MULTIMERIZING IN AN AQUEOUS SOLUTION THAT EMPLOY BIOORTHOGONAL CHEMISTRIES, AND METHODS OF USING SAME - Described herein are monomers capable of forming a biologically useful multimer when in contact with one, two, three or more other monomers in an aqueous media. In one aspect, such monomers may be capable of binding to another monomer in an aqueous media (e.g. in vivo) to form a multimer, (e.g. a dimer). Contemplated monomers may include a ligand moiety, a linker element, and a connector element that joins the ligand moiety and the linker element. In an aqueous media, such contemplated monomers may join together via each linker element and may thus be capable of modulating one or more biomolecules substantially simultaneously, e.g., modulate two or more binding domains on a protein or on different proteins. | 03-26-2015 |
Patent application number | Description | Published |
20090093375 | DNA or RNA detection and/or quantification using spectroscopic shifts or two or more optical cavities - A spectroscopic technique for high-sensitivity, label free DNA quantification uses a shift in an optical resonance (whispering gallery mode, WGM) excited in a micron-sized optical cavity (e.g., a silica sphere) to detect and measure nucleic acids. The surface of the silica sphere is chemically modified with oligonucleotides. Hybridization to the target DNA leads to a red-shift of the optical resonance wavelength. The sensitivity of this resonance technique is higher than most optical single-pass devices such as surface plasmon resonance biosensors. Each microsphere can be identified by its unique resonance wavelength. Specific, multiplexed DNA detection may be provided by using two or more microspheres. The multiplexed signal from two or more microspheres illustrates that a single nucleotide mismatch in an 11-mer oligonucleotide can be discriminated with a high signal-to-noise of 54. This all-photonic WGM biosensor can be integrated on a chip, such as a semiconductor chip, which makes it an easy to manufacture, analytic component for a portable, robust lab-on-a-chip device. | 04-09-2009 |
20100297363 | FUNCTIONALIZING A SENSING RIBBON ON A WHISPERING GALLERY MODE MICRORESONATOR USING LIGHT FORCE TO FABRICATE A WHISPERING GALLERY MODE SENSOR - Methods using light force to fabricate WGM sensors including microresonators having target receptors selectively and substantially provided at only ribbon area of the microresonators. | 11-25-2010 |
20110306854 | SYRINGE-BASED WHISPERING GALLERY MODE MICRORESONATOR MICROFLUIDIC BIOCHEM SENSOR - A syringe-based whispering gallery mode sensor includes a syringe including an assembly provided its needle, the assembly including ( | 12-15-2011 |
20120069331 | PLASMONIC ENHANCEMENT OF WHISPERING GALLERY MODE BIOSENSORS - A sensor for determining the presence or concentration of a target entity in a medium is described, and includes (a) an optical waveguide; (b) a microresonator optically coupled with the optical waveguide such that light within the optical waveguide induces a resonant mode within the microresonator at an equator region (or a mode volume); and (c) at least one plasmonic nanoparticle adsorbed onto a surface area of the microresonator within the equator region (or the mode volume) such that light inducing a resonant mode within the microresonator also causes a plasmonic resonance in the at least one plasmonic nanoparticle. Detection methods for using such sensors are also described. Finally, methods, involving the use of carousel forces, for fabricating such sensors are also described. | 03-22-2012 |
Patent application number | Description | Published |
20090024038 | Acoustic imaging probe incorporating photoacoustic excitation - Various embodiments of the present invention provide for a photoacoustic imaging probe for use in a photoacoustic imaging system, whereby the probe is comprised of a cohesive composite, acoustic lens incorporating aspheric geometry and exhibiting low or practically no measurable dispersion of acoustic waves constructed of at least one material with a low acoustic impedance and attenuation and a relatively low acoustic velocity and at least one other material with a low acoustic impedance and attenuation and a relatively high acoustic velocity. The probe is housed in a conduit filled with a low acoustic velocity and low acoustic impedance fluid such as water or mineral oil. The lens may be designed as a telecentric lens, an acoustic zoom lens, a catadioptric lens, or a reflective lens. The lens focuses acoustic waves on an acoustic imager which detects the image. The acoustic imager may be designed as a 2 dimensional array of transducers. Research to date indicates that within the range of acoustic frequencies of interest, 1 MHz-50 MHz and preferable 2 MHz-10 MHz, there exists little velocity variation within the materials of interest, and the lens design approach may currently be considered to be essentially monochromatic. The acoustic waves can be generated when an emitting light source illuminates a test subject comprising materials that generate acoustic waves at differing intensities and/or frequencies when illuminated with light, for example tissue containing blood vessels, wherein the blood vessels excite and generate an acoustic pulse. The probe has an acoustic window made of a material with low acoustic impedance which allows the acoustic pulse to enter the probe without distortion and then may be reflected by a mirror onto the acoustic lens. The probe may include the emitting light source and an optical window to allow light emitting from said light source to illuminate the test subject. | 01-22-2009 |
20110122060 | OPTICAL NAVIGATION DEVICE - An optical navigation device that can sense the movement of an object, such as a user's finger, so that the movement can control a feature of a consumer digital device such as a cursor on a display screen. The device includes a substrate to which an LED, reflector, and image sensor are attached. Light from the LED is directed by the elliptical reflector toward and through a window that is transparent to the light from the LED and then is reflected off of the user's finger back through the window, through a lens, and onto the image sensor. The reflector is positioned to direct light toward the window at an oblique angle, in the range of 65 to 70 degrees from an angle normal to the window. Further, the reflector is curved to gather light across a large solid angle in the vicinity of the LED. The curved shape of the reflector may be a portion of an ellipsoid and the LED may be located at one of the foci of the ellipsoid, with the window located at the other foci of the ellipsoid. | 05-26-2011 |
20120289813 | Acoustic Imaging Probe Incorporating Photoacoustic Excitation - Embodiments of the present invention provide for a photoacoustic imaging probe for use in a photoacoustic imaging system, said probe comprising a cohesive composite acoustic lens incorporating aspheric geometry and exhibiting low or practically no measurable dispersion of acoustic waves constructed of at least one material with a low acoustic impedance and attenuation and a relatively low acoustic velocity and at least one other material with a low acoustic impedance and attenuation and a relatively high acoustic velocity is immersed in preferably a low acoustic velocity and low acoustic impedance fluid. The lens may be designed as an acoustic reflective lens or an acoustic lens incorporating spheric geometry. The lens focuses acoustic waves on an acoustic imager which detects the image. The lens may be considered to be essentially monochromatic. | 11-15-2012 |
20140113383 | FULL RESOLUTION COLOR IMAGING OF AN OBJECT - The invention relates generally to both a method and apparatus for the creation of full resolution color digital images of diagnostic cassettes or objects of interest using a gray-scale digital camera or sensor combined with time sequential illumination using additive primary colors followed by post exposure digital processing. Such procedures and equipment is of significant economic value when employed in situations such as diagnostic clinical analyzers where space is limited and image quality requirements are high. | 04-24-2014 |
20140320410 | OPTICAL NAVIGATION DEVICE - An optical navigation device that can sense the movement of an object, such as a user's finger, so that the movement can control a feature of a consumer digital device such as a cursor on a display screen. The device includes a substrate to which an LED, reflector, and image sensor are attached. Light from the LED is directed by the elliptical reflector toward and through a window that is transparent to the light from the LED and then is reflected off of the user's finger back through the window, through a lens, and onto the image sensor. The reflector is positioned to direct light toward the window at an oblique angle, in the range of 65 to 70 degrees from an angle normal to the window. Further, the reflector is curved to gather light across a large solid angle in the vicinity of the LED. The curved shape of the reflector may be a portion of an ellipsoid and the LED may be located at one of the foci of the ellipsoid, with the window located at the other foci of the ellipsoid. | 10-30-2014 |
Patent application number | Description | Published |
20080256633 | Method and Apparatus for Determination of the Non-Replicative Behavior of a Malicious Program - Disclosed is a method, a computer system and a computer readable media product that contains a set of computer executable software instructions for directing the computer system to execute a process for determining a non-replicative behavior of a program that is suspected of containing an undesirable software entity. The process causes execution of the program in at least one known environment and automatically examines the at least one known environment to detect if a change has occurred in the environment as a result of the execution of the program. If a change is detected, the process automatically analyzes the detected change (i.e., the process performs a side effects analysis) to determine if the change resulted from execution of the program or from execution of the undesirable software entity. The process then uses the result of the analysis at least for undoing a detected change that results from execution of the undesirable software entity. The result of the analysis can also be used for informing a user of an anti-virus system of the non-replicative changes made to the environment. | 10-16-2008 |
20080301630 | MECHANISM TO PROVIDE DEBUGGING AND OPTIMIZATION IN POLICY AND KNOWLEDGE CONTROLLED DISTRIBUTED COMPUTING SYSTEMS, THROUGH THE USE OF TAGGED POLICIES AND KNOWLEDGE REPRESENTATION ELEMENTS - A mechanism to provide debugging and optimization in policy and knowledge controlled distributed computing system through the use of tagged policies is provided. An aspect of the mechanism tags one or more policies, for instance, at their creation time, execution time and/or at any other time an event that affects the policies occur. Decisions made according to policy execution or evaluation may be traced using the tags. | 12-04-2008 |
20090307747 | System To Establish Trust Between Policy Systems And Users - A system and method are provided to establish trust between a user and a policy system that generates recommended actions in accordance with specified policies. Trust is introduced into the policy-based system by assigning a value to each execution of each policy with respect to the policy-based system, called the instantaneous trust index. The instantaneous trust indices for each one of the policies, for the each execution of a given policy or for both are combined into the overall trust index for a given policy or for a given policy-based system. The recommended actions are processed in accordance with the level or trust associated with a given policy as expressed by the trust indices. Manual user input is provided to monitor or change the recommended actions. In addition, reinforcement learning algorithms are used to further enhance the level of trust between the user and the policy-based system. | 12-10-2009 |
20090319239 | TOPOLOGY MODELING APPLICATION THAT HANDLES ABSTRACT ENTITIES THROUGH THE REALIZATION OF CONCEPTUAL OBJECTS - The present invention can include a solution for handling abstract entities through the realization of conceptual objects within a modeling application. Such a system can include a semantic model and a modeling application. The semantic model can be configured to present relationships between entities. The entities can include both conceptual objects and concrete objects. A conceptual object can represent an abstract definition that can contain unfulfilled functional parameters. The conceptual object can be associated with another conceptual object or concrete object using a realization relationship. The modeling application can be configured to handle conceptual objects and realization relationships, while preserving the relational integrity of the semantic model. | 12-24-2009 |
20100031247 | SIMPLIFIED DEPLOYMENT MODELING - A deployment modeling platform enables a user to model application characteristics of target software and to associate application modeling parameters to the modeled application characteristics. A user may also model environment characteristics of a target deployment environment and to associate environment modeling parameters to the modeled deployment environment characteristics. Still further, a user may create a deployment model that associates and maps selected parameters of the modeled application characteristics of the target software to associated parameters of the modeled environment characteristics of the deployment environment, and to verify that each parameter that relates to a requirement is mapped to and is fulfilled by an associated parameter that relates to a corresponding capability to determine whether validation problems exist in order to deploy the target software in the associated deployment environment. | 02-04-2010 |
20100070449 | DEPLOYMENT PATTERN REALIZATION WITH MODELS OF COMPUTING ENVIRONMENTS - Deployment pattern matching is implemented by accessing a target computing environment model that captures environment modeling parameters relating to resources and resource-resource relationships of a corresponding computing environment and expressing the target computing environment model as a model graph defined by target resource elements and resource-to-resource relationship links. Deployment pattern matching is further implemented by accessing a realization pattern that captures deployment parameters relating to resources and resource-resource relationships of a deployment of interest and expressing the realization pattern as a pattern graph defined by conceptual resource elements and constraints arranged by resource-to-resource relationship links and constraint links. The realization pattern is then evaluated against the target computing environment model by executing at least one pattern matching algorithm that attempts to match the pattern graph to the model graph and information corresponding to results of the evaluation are conveyed. | 03-18-2010 |
20120192146 | SIMPLIFIED DEPLOYMENT MODELING - A deployment modeling platform enables a user to model application characteristics of target software and to associate application modeling parameters to the modeled application characteristics. A user may also model environment characteristics of a target deployment environment and to associate environment modeling parameters to the modeled deployment environment characteristics. Still further, a user may create a deployment model that associates and maps selected parameters of the modeled application characteristics of the target software to associated parameters of the modeled environment characteristics of the deployment environment, and to verify that each parameter that relates to a requirement is mapped to and is fulfilled by an associated parameter that relates to a corresponding capability to determine whether validation problems exist in order to deploy the target software in the associated deployment environment. | 07-26-2012 |
Patent application number | Description | Published |
20100306772 | VIRTUAL SOLUTION COMPOSITION AND DEPLOYMENT SYSTEM AND METHOD - A method and information processing system are provided for creating a virtual part and for composing and deploying a virtual solution with one or more virtual parts. The virtual part includes: a virtual image including a set of compatible software components; a set of configurability points, each configurability point defining at least one parameter of the virtual part that is configurable; a set of virtual ports, wherein each virtual port indicates at least one of a set of virtual parts required by the virtual part and a set of virtual parts that are compatible with the virtual part; and a set of configuration scripts adapted to reconfigure the virtual image. | 12-02-2010 |
20120081395 | DESIGNING AND BUILDING VIRTUAL IMAGES USING SEMANTICALLY RICH COMPOSABLE SOFTWARE IMAGE BUNDLES - A virtual image is created by receiving a selection of at least one composable software bundle. The at least one composable software bundle includes a first set of metadata and a first set of artifacts comprising a first set of executable instructions associated with a first set of operations. A virtual image asset is selected and received. The virtual image asset includes one or more virtual image disks, a second set of metadata, and a second set of artifacts including a second set of executable instructions associated with a second set of operations. A new virtual image asset is created based on the at least one composable software bundle and the virtual image asset. The new virtual image asset includes a third set of metadata that is based on the first set of metadata and the second set of metadata. | 04-05-2012 |
20120084769 | SEMANTICALLY RICH COMPOSABLE SOFTWARE IMAGE BUNDLES - A composable software bundle is created by retrieving a semantic representation of a set of software modules. A functional representation of a set of operations is retrieved. Each operation in the set of operations is to be performed on the set of software modules during at least one virtual image life-cycle phase in a set of virtual image life-cycle phases. A set of artifacts including a set of executable instructions associated with the set of operations is identified. The semantic representation, the functional representation, and the set of artifacts, are stored in a composable software bundle. | 04-05-2012 |
20120304174 | VIRTUAL SOLUTION COMPOSITION AND DEPLOYMENT SYSTEM AND METHOD - Various embodiments disclose a method and system for creating a virtual part used for composing a virtual solution. In one embodiment, a user's selection of at least one virtual image is received. A set of configurability points is associated with the virtual image. A set of parameters of a virtual part is set as configurable during virtual solution composition. A set of virtual ports is generated. Each virtual port within the set of virtual ports indicates at least one of a set of virtual parts required by a virtual part including the set of virtual ports and a set of virtual parts that is compatible with the virtual part. A set of configuration operations is received. A virtual part including at least the virtual image, the set of configurability points, the set of virtual ports, and the configuration operations is generated. | 11-29-2012 |
20130007745 | IMAGE ASSET LIFECYCLE MANAGEMENT IN A COMPUTING ENVIRONMENT - Lifecycles of virtual image assets are managed as follows. A set of assets including a set virtual image assets and a set of software bundle assets are analyzed. At least a portion of relationship data between one or more of the virtual image assets and one or more of the software bundle assets is determined. The at least a portion of relationship data is stored in a memory. At least one of one or more virtual image assets and one or more software bundle assets are determined to be associated with a set of changes. At least one virtual image asset that is related to the one or more virtual image assets and/or one or more software bundle assets associated with the set of changes is identified. The at least one virtual image asset that has been identified is updated based on the set of changes. | 01-03-2013 |
20130179390 | DEPLOYMENT PATTERN REALIZATION WITH MODELS OF COMPUTING ENVIRONMENTS - Deployment pattern matching is implemented by accessing a target computing environment model that captures environment modeling parameters relating to resources and resource-resource relationships of a corresponding computing environment and expressing the target computing environment model as a model graph defined by target resource elements and resource-to-resource relationship links. Deployment pattern matching is further implemented by accessing a realization pattern that captures deployment parameters relating to resources and resource-resource relationships of a deployment of interest and expressing the realization pattern as a pattern graph defined by conceptual resource elements and constraints arranged by resource-to-resource relationship links and constraint links. The realization pattern is then evaluated against the target computing environment model by executing at least one pattern matching algorithm that attempts to match the pattern graph to the model graph and information corresponding to results of the evaluation are conveyed. | 07-11-2013 |